Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
8.3.6.4
Setup Error Bit – D4
The SETUP ERROR identifies byte programming and page erase setup errors. Setup errors specifically
apply to Type 2 CSI commands (see Section 8.3.5, "CSI Command Types"). When the SETUP ERROR
bit is deasserted ‘0’, assuming the bit was cleared initially, the argument cycle for a Type 2 command
has been completed successfully. When the SETUP ERROR bit is asserted ‘1’, a Type 2 PROGRAM
BYTE or ERASE PAGE command code cycle has been followed by a read bus cycle instead of a write
(argument) cycle. (see Section 8.3.7.10, "CSI Host Interface Error Handling").
8.3.6.5
Info Bit – D3
The INFO identifies whether the Main Memory or Information Memory is selected in the Flash Memory
Array (see the SET MAIN BLOCK ACCESS and SET INFO BLOCK ACCESS CSI command codes in
Table 8.6 and Section 8.3.7, "CSI State Sequencing").
When Information Memory is selected, the CSI status register INFO bit is asserted ‘1’. When Main
Memory is selected, the CSI status register INFO bit is deasserted ‘0’. The Main Memory is selected
by default following VCC1 POR and nRESET.
The INFO bit is not affected by the CLEAR STATUS command.
8.3.6.6
Lock Bit – D2
The LOCK bit D2 in the CSI status register is the inverse of the nWRTPRT input (see Section 8.4, "Flash
Write Protect"). When the nWRTPRT input is ‘1’, i.e. the boot block is not write-protected (unlocked),
the CSI status register LOCK bit is ‘0’. When the nWRTPRT input is ‘0’, i.e. the boot block is write-
protected (locked), the CSI status register LOCK bit is ‘1’. The LOCK bit is not affected by the CLEAR
STATUS command and is not affected by VCC1 POR or nRESET; i.e., there is no LOCK bit default.
8.3.7
CSI State Sequencing
8.3.7.1
Overview
CSI state sequencing implies two independent and concurrent processes: the host interface function and
the flash interface function (Figure 8.2). The CSI host interface function is illustrated in Figure 8.3. The
host interface handles user commands for the flash interface so that, for example, a MASS ERASE
operation can be executed by the flash interface while the host interface transitions to a state that allows
to the initiator to measure the operation progress.
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA9S5HEET
SMSC [ SMSC CORPORATION ]
