Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
IFREN
XADR
XE
MAS1
Trcv
Tnvh1
ERASE
NVSTR
Tnvs
Tme
Figure 8.7 Flash Core Mass Erase Timing Diagram
Table 8.12 Flash Core Mass Erase Timing Values
NAME
MIN
MAX
UNITS
COMMENT
Tnvs
Tnvh1
Trcv
5
100
1
µs
PROG/ERASE to NVSTR set up time
NVSTR hold time
Recovery time
Tme
2
4
ms
Mass erase time
8.3.7.6
Read Status (Idle) Mode
The Read Status Mode uses the CSI host interface to disconnect the flash memory array from the DOUT
bus and makes the CSI status register available for subsequent host read cycles (Figure 8.3). Assuming
all program operations are complete, the CSI flash interface sets the Flash Memory Array interface
signals to the standby mode for the duration of the Read Status mode. The CSI host interface and the
Flash Memory Array remain in the Read Status (Idle) mode indefinitely until the next command is given.
In Read Status mode, write cycles to the 64k Embedded Flash Host Interface program the CSI
command register (not shown in Figure 8.3).
8.3.7.7
Clear Status Mode
The Clear Status Mode uses the CSI host interface to disconnect the flash memory array from the DOUT
bus, deasserts the status register error bits (Table 8.8), and makes the CSI status register available for
subsequent host read cycles (Figure 8.3). The CSI flash interface sets the Flash Memory Array signals
to the standby mode for the duration of the Clear Status mode. The CSI host interface and the Flash
Memory Array interface remain in the Read Status (Idle) mode until the next command is given.
Revision 1.1 (01-14-03)
100
SMSC LPC47N350
DATASHEET