ST7578
PS2= "L", PS1= "L", PS0= "L" : 4-line SPI interface
When ST7578 is active (CSB=“L”), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7578 is not
active (CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. The display data/command indication is
controlled by the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and
will be instruction when A0 is low. The read feature is not supported in this mode. Serial data on SDA is latched at the rising
edge of serial clock on SCLK. After the 8th serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM
column address pointer will be increased by one automatically after each byte of DDRAM access.
Fig 4. 4-Line SPI Access
PS2= "L", PS1= "L", PS0= "H": 3-line SPI interface
When ST7578 is active (CSB=“L”), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7578 is not
active (CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. The A0 pin is not available in this mode. Before
issuing serial data, an A0 bit is required to indicate the following 8-bit signals are data or instruction. The read feature is not
supported in this mode. Serial data on SDA is latched at the rising edge of serial clock on SCLK. After the 9th serial clock,
the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one
automatically after each byte of DDRAM access.
Fig 5. 3-Line SPI Access
Ver 1.2
19/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
