ST7578
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the DDRAM. The display data RAM
column address is specified by the Column Address Set command. The specified column address is incremented (+1) with
each display data read/write command. This allows the MPU display data to be accessed continuously.
Register MX and MY makes it possible to invert the relationship between the addresses (Line Address and Column Address)
and the outputs (COM/SEG). It is necessary to rewrite the display data into built-in RAM after changing MX setting.
The relation between DDRAM and outputs with different MX or MY setting is shown below.
Column Address (Hex)
MX=0
MX=1
COM Output Map
1/66 Duty
PAD No.
Page Address
Data
(DO=0)
D3 D2 D1 D0
MY=0
MY=1
(COM)
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
163
162
161
160
159
158
157
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
B
B
B
B
B
B
B
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM64
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
B
B
B
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
B
B
B
B
B
B
B
B
B
B
B
B
B
B
COM10 COM54
COM11 COM53
COM12 COM52
COM13 COM51
COM14 COM50
COM15 COM49
COM16 COM48
COM17 COM47
COM18 COM46
COM19 COM45
COM20 COM44
COM21 COM43
COM22 COM42
COM23 COM41
COM24 COM40
COM25 COM39
COM26 COM38
COM27 COM37
COM28 COM36
COM29 COM35
COM30 COM34
COM31 COM33
COM32 COM32
COM33 COM31
COM34 COM30
COM35 COM29
COM36 COM28
COM37 COM27
COM38 COM26
COM39 COM25
COM40 COM24
COM41 COM23
COM42 COM22
COM43 COM21
COM44 COM20
COM45 COM19
COM46 COM18
COM47 COM17
COM48 COM16
COM49 COM15
COM50 COM14
COM51 COM13
COM52 COM12
COM53 COM11
COM54 COM10
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
10
9
8
7
B
6
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
5
4
3
2
B
B
B
B
B
B
B
B
B
1
244
245
246
247
B
B
B
B
1
1
0
0
0
0
0
1
D7
D7
40H
41H
COM64
COM0
248
Page 8
Page 9
ICON
(COMS1, COMS2)
130, 243
PAD No.
(SEG)
Fig 8. Relationship between DDRAM and Outputs (COM/SEG)
Ver 1.2
22/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
