ST7578
Power System Pins
Pin Name
Type
Description
No. of Pins
4
Digital ground. Connect to VSS2 externally.
VSS1
Power
For pins that are set to be “L”, connect them to this power (use VSS1 for “L”).
Analog ground. Connect to VSS1 externally.
VSS2
Power
Power
6
3
VDX2O
Power for test mode. Left this pin floating.
Digital power. If VDD1=VDD2, connect to VDD2 externally.
For pins that are set to be “H”, connect them to this power (use VDD1 for “H”).
Analog power. If VDD1=VDD2, connect to VDD1 externally.
LCD driving voltage for commons at negative frame.
V0 ≥ VG > VM > VSS ≥ XV0
VDD1
VDD2
Power
Power
5
4
V0
Power
Power
Power
7
7
7
(V0O, V0I, V0S)
V0O, V0I & V0S should be separated in ITO layout.
V0O, V0I & V0S should be connected together in FPC layout.
LCD driving voltage for commons at positive frame.
XV0O, XV0I & XV0S should be separated in ITO layout.
XV0O, XV0I & XV0S should be connected together in FPC layout.
LCD driving voltage for segments.
XV0
(XV0O, XV0I,
XV0S)
VG
VGO, VGI & VGS should be separated in ITO layout.
VGO, VGI & VGS should be connected together in FPC layout.
1.24 ≤ VG < VDD2.
(VGO, VGI, VGS)
VM output. LCD driving voltage for commons.
VMO
VRS
CP
Power
Power
I
4
1
1
0.62V ≤ VM < VDD2.
Test pin for monitoring voltage reference level.
This pin must be left open (without any kinds of connection).
Booster configuration pin for default setting : “L”=4X; “H”=5X.
This pin set the default booster stage after reset.
Bias circuit configuration pin for default setting : “L”=1/7; “H”=1/9.
This pin set the default value of bias ratio after reset.
The bias ratio can be changed by software instruction.
BR
I
1
Test Pins
Pin Name
Type
T
Description
Do NOT use. Reserved for testing.
Must be floating.
No. of Pins
11
T0~T10
T11
Do NOT use. Reserved for testing.
Must be “L”. Connect to VSS1 for pull-low.
Do NOT use. Reserved for testing.
Must be “H”. Connect to VDD1 for pull-high.
T
T
1
1
T12
Ver 1.2
16/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
