ST7578
6. FUNCTIONS DESCRIPTION
Microprocessor Interface
Chip Select Input
CSB pin is used for chip selection. ST7578 can interface with an MPU when CSB is "L". When CSB is “H”, the inputs of A0,
ERD and RWR with any combination will be ignored and D[7:0] are high impedance. In 3-Line and 4-Line serial interface,
the internal shift register and serial counter are reset when CSB is “H”.
Parallel / Serial Interface
ST7578 has five types of interface for kinds of MPU, which are three serial and two parallel interfaces. The selection for
parallel or serial interface is determined by PS[2:0] pins as shown in table 1.
Table 1. Parallel/Serial Interface Mode
PS2
PS1
PS0
CSB
A0
ERD
RWR
D[7:0]
MPU Interface
“L”
“H”
“L”
“H”
“L”
“L”
“H”
“H”
“L”
“L”
“L”
“L”
A0
---
4-Line SPI interface
3-Line SPI interface
8080-series parallel interface
6800-series parallel interface
CSB
---
---
Refer to serial interface.
/RD
E
/WR
R/W
CSB
A0
D[7:0]
* The un-used pins are marked as “---” and should be fixed to “H” by VDD1.
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 as shown in table 2.
The data transfer type is determined by signals of A0, ERD and RWR as shown in table 3.
Table 2. Microprocessor Selection for Parallel Interface
PS2
PS1
PS0
CSB
A0
ERD
RWR
D[7:0]
MPU Interface
“L”
“H”
“H”
“H”
“L”
“L”
/RD
E
/WR
R/W
8080-series
6800-series
CSB
A0
D[7:0]
Table 3. Parallel Data Transfer
8080-series
Common
6800-series
Description
A0
E (ERD)
R/W (RWR) /RD (ERD) /WR (RWR)
“H”
“H”
“L”
“L”
“H”
“H”
“H”
“H”
“H”
“L”
“H”
“L”
“L”
“H”
“L”
“H”
“H”
“L”
“H”
“L”
Display data read out
Display data write
Internal status read
Writes to internal register (instruction)
NOTE: In 6800-series interface mode, fixing E (ERD) pin at high can use CSB as enable signal instead. In this case,
interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0 and R/W
(RWR) pins as defined in 6800-series mode.
Setting Serial Interface
Serial Mode
PS[2:0] CSB
A0
ERD RWR
D[7:0]
4-Line SPI interface “L, L, L”
3-Line SPI interface “H, L, L”
A0
---
CSB
--- --- ---, ---, ---, ---, SDA, SDA, SDA, SCLK
* The un-used pins are marked as “---” and should be fixed to “H” by VDD1.
Note:
1. The option setting to be “H” should connect to VDD1.
2. The option setting to be “L” should connect to VSS1.
Ver 1.2
18/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
