ST7578
Recommend ITO Resistance
Pin Name
ITO Resistance
Floating
< 100Ω
T[0:10], VRS, VDX2O
VDD1, VDD2, VSS1, VSS2
V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VMO
< 300Ω
A0, RWR, ERD, CSB, D[7:0] *1
< 1KΩ
PS[2:0], OSC *2, CP, BR, T11, T12
< 5KΩ
RESB *3
< 10KΩ
Note:
1. If using 3-Line or 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 500Ω.
2. If using internal clock, OSC is connect to VDD1 and the limitation of ITO resistance will be “No Limitation”.
If using external clock, the ITO resistance of OSC should be kept lower than 300Ω to keep the clock signal quality.
3. To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RESB signal
(add a series resistor or increase ITO resistance). The value is different from modules.
4. The option setting to be “H” should connect to VDD1.
5. The option setting to be “L” should connect to VSS1.
Ver 1.2
17/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
