ST2202A
18. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER
BGRꢀcontrolꢀregisterꢀBCTR.ꢀSettingsꢀofꢀclockꢀoutputꢀofꢀ
TheꢀST2202ꢀintegratesꢀoneꢀuniversalꢀasynchronousꢀ
receiver/transmitterꢀ(UART),ꢀwhichꢀcanꢀbeꢀusedꢀtoꢀ
communicateꢀwithꢀexternalꢀserialꢀdevices.ꢀSerialꢀdataꢀisꢀ
transmittedꢀandꢀreceivedꢀatꢀstandardꢀbitꢀratesꢀusingꢀtheꢀ
internalꢀbaudꢀrateꢀgeneratorꢀ(BGR),ꢀwhichꢀisꢀcontrolledꢀbyꢀ
ꢀ
BGRꢀ(BGRCK)ꢀcanꢀbeꢀfoundꢀinꢀsectionꢀ11.ꢀFIGUREꢀ18ꢁ1ꢀ
showsꢀtheꢀblockꢀdiagramꢀofꢀUART.ꢀSummaryꢀofꢀUARTꢀ
controlꢀregistersꢀisꢀlistedꢀinꢀTABLEꢀ18ꢁ1.ꢀ
CPUꢀInterface
TXD1
RXD1
Transmitter
Receiver
Serial
Interface
TXD0
RXD0
IrDA
Interface
BaudꢀRate
Generator
ꢀ
FIGURE 18-1 UART Block Diagram
ꢀ
TABLE 18-1 Summary Of UART Control Registers
Address Name
$060 UCTR
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PMODꢀ UMODꢀ
TXBZꢀ
Bit 1
Bit 0
Default
R/Wꢀ
Rꢀ
Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
FERꢀ
ꢁꢀ
ꢁꢀ
PERꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
OERꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
PENꢀ
RXBZꢀ RXENꢀ
RXTRGꢀ RXENꢀ TXTRGꢀ TXENꢀ
BRKꢀ
TXENꢀ
ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢁ000ꢀ0000ꢀ
ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
00ꢁꢀꢁꢀꢁ000ꢀ
$061 USTR
$062 IRCTR
$063 BCTR
$064 UDATA
$066 BRS
$067 BDIV
$00A PCC
$00B PCD
$00D PFC
$00E PFD
$03D IREQH
$03F IENAH
R/Wꢀ RXINVꢀ TXINVꢀ
R/Wꢀ TESTꢀ
R/Wꢀ UD[7]ꢀ
R/Wꢀ BRS[7]ꢀ BRS[6]ꢀ BRS[5]ꢀ BRS[4]ꢀ BRS[3]ꢀ BRS[2]ꢀ BRS[1]ꢀ BRS[0]ꢀ ????ꢀ????ꢀ
R/Wꢀ BDIV[7]ꢀ BDIV[6]ꢀ BDIV[5]ꢀ BDIV[4]ꢀ BDIV[3]ꢀ BDIV[2]ꢀ BDIV[1]ꢀ BDIV[0]ꢀ ????ꢀ????ꢀ
R/Wꢀ PCC[7]ꢀ PCC[6]ꢀ PCC[5]ꢀ PCC[4]ꢀ PCC[3]ꢀ PCC[2]ꢀ PCC[1]ꢀ PCC[0]ꢀ 0000ꢀ0000ꢀ
R/Wꢀ PCD[7]ꢀ PCD[6]ꢀ PCD[5]ꢀ PCD[4]ꢀ PCD[3]ꢀ PCD[2]ꢀ PCD[1]ꢀ PCD[0]ꢀ 0000ꢀ0000ꢀ
R/Wꢀ RXD0ꢀ
R/Wꢀ RXD1ꢀ
ꢁꢀ
ꢁꢀ
PW1ꢀ
PW0ꢀ
IRENꢀ
ꢁꢀ
BSTRꢀ BMODꢀ BGRENꢀ 0ꢁꢀꢁꢀꢁꢀꢁ000ꢀ
UD[2]ꢀ UD[1]ꢀ UD[0]ꢀ ????ꢀ????ꢀ
UD[6]ꢀ
UD[5]ꢀ
UD[4]ꢀ
UD[3]ꢀ
TXD0ꢀ
TXD1ꢀ
ꢁꢀ
SRDYꢀ
CS6ꢀ
SSꢀ
CS5ꢀ
ꢁꢀ
MOSIꢀ
CS4ꢀ
MISOꢀ
CS3ꢀ
SCKꢀ
CS2ꢀ
INTXꢀ
CS1ꢀ
0000ꢀ0000ꢀ
0000ꢀ0000ꢀ
R/Wꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
IRURXꢀ IRUTXꢀ IRSRXꢀ IRSTXꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000
IEURXꢀ IEUTXꢀ IESRXꢀ IESTXꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢁꢀ
ꢁꢀ
ꢀ
ꢀ
18.2 UART Operations
TheꢀUARTꢀhasꢀtwoꢀmodesꢀofꢀoperation,ꢀNRZꢀandꢀIrDA,ꢀ
communicationꢀprotocols,ꢀRSꢁ232ꢀandꢀIrDA.
whichꢀrepresentꢀdataꢀinꢀdifferentꢀwaysꢀforꢀserialꢀ
ꢀ
18.2.1 NRZ mode
18.2.2 IrDA mode
Theꢀnonꢁreturnꢀtoꢀzeroꢀ(NRZ)ꢀmodeꢀisꢀprimarilyꢀassociatedꢀ
withꢀRSꢁ232.ꢀEachꢀcharacterꢀisꢀtransmittedꢀasꢀaꢀframeꢀ
delimitedꢀbyꢀaꢀstartꢀbitꢀatꢀtheꢀbeginningꢀandꢀaꢀstopꢀbitꢀatꢀtheꢀ
end.ꢀDataꢀbitsꢀareꢀtransmittedꢀleastꢀsignificantꢀbitꢀ(LSB)ꢀfirst,ꢀ
andꢀeachꢀbitꢀoccupiesꢀaꢀperiodꢀofꢀtimeꢀequalꢀtoꢀ1ꢀfullꢀbit.ꢀIfꢀ
parityꢀisꢀused,ꢀtheꢀparityꢀbitꢀisꢀtransmittedꢀafterꢀtheꢀmostꢀ
significantꢀbit.ꢀDataꢀsettingsꢀincludingꢀdataꢀlength,ꢀstopꢀbitꢀ
numberꢀandꢀparityꢀareꢀcontrolledꢀbyꢀbitꢀfieldsꢀinꢀUCTR.ꢀ
FIGUREꢀ18ꢁ2ꢀillustratesꢀaꢀcharacterꢀ“S”ꢀinꢀNRZꢀmode.ꢀ
ꢀ
IrDAꢀmodeꢀusesꢀcharacterꢀframesꢀasꢀNRZꢀmodeꢀdoes,ꢀbut,ꢀ
insteadꢀofꢀdrivingꢀonesꢀandꢀzerosꢀforꢀaꢀfullꢀbitꢁtimeꢀperiod,ꢀ
zerosꢀareꢀtransmittedꢀasꢀthreeꢁsixteenthꢀ(orꢀless)ꢀbitꢁtimeꢀ
pulsesꢀ(whichꢀisꢀselectedꢀbyꢀPW[1:0]ꢀ(IRCTR[2:1]),ꢀandꢀ
onesꢀremainꢀlow.ꢀTheꢀpolarityꢀofꢀtransmittedꢀpulsesꢀandꢀ
expectedꢀreceiveꢀpulsesꢀcanꢀbeꢀinvertedꢀsoꢀthatꢀaꢀdirectꢀ
connectionꢀcanꢀbeꢀmadeꢀtoꢀexternalꢀIrDAꢀtransceiverꢀ
modulesꢀthatꢀuseꢀactiveꢀlowꢀpulses.ꢀThisꢀisꢀcontrolledꢀbyꢀ
RXINVꢀandꢀTXINVꢀ(IRCTR[7:6]).ꢀIrDAꢀmodeꢀisꢀenabledꢀbyꢀ
controlꢀbitꢀIRENꢀ(IRCTR[0]).ꢀFIGUREꢀ18ꢁ3ꢀillustratesꢀaꢀ
characterꢀ“S’ꢀinꢀIrDAꢀmode.ꢀ
ꢀ
Verꢀ2.5ꢀ
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9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
