ST2202A
17.3 SPI Control/Status Registers
SPIꢀcontrolꢀandꢀstatusꢀregistersꢀareꢀsummarizedꢀinꢀTABLEꢀ17ꢁ1.ꢀ
ꢀ
TABLE 17-2 Summary Of SPI Control Registers
Address Name
R/W Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8
Default
$050 SDATAL
$051 SDATAH
$052 SCTR
R/Wꢀ SD[7]ꢀ
SD[6]ꢀ
SD[5]ꢀ
SD[4]ꢀ
SD[3]ꢀ
SD[2]ꢀ
SD[1]ꢀ
SD[0]ꢀ
SD[8]ꢀ
SMODꢀ 0000ꢀ0000ꢀ
BC[0]ꢀ ꢁ000ꢀ0000ꢀ
????ꢀ????ꢀ
????ꢀ????ꢀ
R/Wꢀ SD[15]ꢀ SD[14]ꢀ SD[13]ꢀ SD[12]ꢀ SD[11]ꢀ SD[10]ꢀ SD[9]ꢀ
R/Wꢀ SPIENꢀ RXIENꢀ ERIENꢀ MERENꢀ DRINVꢀ
POLꢀ
BC[2]ꢀ
PHAꢀ
BC[1]ꢀ
$053 SCKR
R/Wꢀ
Rꢀ
ꢁꢀ
ꢁꢀ
SCK[2]ꢀ SCK[1]ꢀ SCK[0]ꢀ BC[3]ꢀ
RXRDYꢀ TXEMPꢀ SBZꢀ ꢁꢀ
WriteꢀanyꢀvalueꢀtoꢀresetꢀSSRꢀ
MDERRꢀ OERRꢀ BCERRꢀ ꢁ000ꢀꢁ000ꢀ
$054 SSR
Wꢀ
ꢀ
$00A PCC
$00D PFC
$03D IREQH
$03F IENAH
R/Wꢀ PCC[7]ꢀ PCC[6]ꢀ PCC[5]ꢀ PCC[4]ꢀ PCC[3]ꢀ PCC[2]ꢀ PCC[1]ꢀ PCC[0]ꢀ 0000ꢀ0000ꢀ
R/Wꢀ RXD0ꢀ
TXD0ꢀ
ꢁꢀ
ꢁꢀ
SRDYꢀ
SSꢀ
ꢁꢀ
MOSIꢀ
MISOꢀ
SCKꢀ
INTXꢀ
0000ꢀ0000ꢀ
R/Wꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
IRURXꢀ IRUTXꢀ IRSRXꢀ IRSTXꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000
IEURXꢀ IEUTXꢀ IESRXꢀ IESTXꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢁꢀ
ꢀ
ꢀ
17.3.1 SPI Data Registers
TABLE 17-3 SPI Data Registers
Address Name R/W Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9
Bit 0/8
Default
$050 SDATAL
$051 SDATAH
R/Wꢀ SD[7]ꢀ
SD[6]ꢀ
SD[5]ꢀ
SD[4]ꢀ
SD[3]ꢀ
SD[2]ꢀ
SD[1]ꢀ
SD[9]ꢀ
SD[0]ꢀ 0000ꢀ0000ꢀ
SD[8]ꢀ 0000ꢀ0000ꢀ
R/Wꢀ SD[15]ꢀ SD[14]ꢀ SD[13]ꢀ SD[12]ꢀ SD[11]ꢀ SD[10]ꢀ
ꢀ
Bitꢀ ꢀ 7~0:ꢀ ꢀWrite:ꢀWriteꢀlowꢀbyteꢀdataꢀtoꢀtransmitꢀbufferꢀ/ꢀclearꢀstatusꢀbitꢀTXEMPꢀ/ꢀtriggerꢀanꢀdataꢀexchangeꢀ
Read:ꢀReadꢀlowꢀbyteꢀdataꢀfromꢀreceiveꢀbufferꢀ/ꢀclearꢀstatusꢀbitꢀRXRDY
ꢀ
ꢀ
Bitꢀ15~8:ꢀ ꢀ Write:ꢀWriteꢀhighꢀbyteꢀdataꢀtoꢀtransmitꢀbufferꢀ/ꢀRead:ꢀReadꢀhighꢀbyteꢀdataꢀfromꢀreceiveꢀbufferꢀ
17.3.2 SPI Control Register
Address Name R/W Bit 7
ꢀ
TABLE 17-4 SPI Control Register
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Default
$052 SCTR
R/Wꢀ SPIENꢀ RXIENꢀ ERIENꢀ MERENꢀ DRINVꢀ
POLꢀ
PHAꢀ
SMODꢀ 0000ꢀ0000ꢀ
ꢀ
Bitꢀ7:ꢀ ꢀ SPIEN
ꢀ
:ꢀSPIꢀcontrolꢀbitꢀ
0
ꢀ=ꢀSPIꢀdisableꢀ
1ꢀ=ꢀSPIꢀenableꢀ
ꢀ
Bitꢀ6:ꢀ ꢀ RXIEN
ꢀ=ꢀReceiveꢀbufferꢀreadyꢀinterruptꢀdisableꢀ
1ꢀ=ꢀReceiveꢀbufferꢀreadyꢀinterruptꢀenableꢀ
ꢀ:ꢀReceiveꢀbufferꢀreadyꢀinterruptꢀcontrolꢀbitꢀ
0
ꢀ
Bitꢀ5:ꢀ ꢀ ERIEN
ꢀ=ꢀTwoꢀerrorꢀinterruptsꢀdisableꢀ
1ꢀ=ꢀTwoꢀerrorꢀinterruptsꢀenableꢀ
ꢀ:ꢀTwoꢀerrorꢀinterruptsꢀcontrolꢀbitꢀ
0
ꢀ
Bitꢀ4:ꢀ ꢀ MEREN
ꢀ=ꢀModeꢀfaultꢀdetectionꢀdisableꢀ
1ꢀ=ꢀModeꢀfaultꢀdetectionꢀenableꢀ
ꢀ:ꢀModeꢀfaultꢀdetectionꢀcontrolꢀbitꢀ
0
ꢀ
ꢀ
Bitꢀ3:ꢀ ꢀ DRINV :
ꢀ
ꢀ activeꢀlevelꢀselectionꢀbitꢀ
DATA_READY
ꢀ=ꢀActiveꢀlevelꢀisꢀhighꢀ
1ꢀ=ꢀActiveꢀlevelꢀisꢀlowꢀ
0
Bitꢀ2~1:ꢀSPHA/SPOL :ꢀSPIꢀclockꢀpolarityꢀandꢀphaseꢀcontrolꢀbitsꢀ
Referꢀtoꢀsectionꢀ17.1.1ꢀ
ꢀ
Bitꢀ0:ꢀ ꢀ SMOD :ꢀMasterꢀ/ꢀSlaveꢀmodesꢀselectionꢀbitꢀ
0
ꢀ=ꢀSelectꢀslaveꢀmodeꢀ
1ꢀ=ꢀSelectꢀmasterꢀmodeꢀ
Verꢀ2.5ꢀ
49
/75
ꢀ
9/16/2008ꢀ
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