ST2202A
pinsꢀalsoꢀinterfaceꢀtoꢀstandardꢀRSꢁ232ꢀandꢀinfraredꢀ
transceiverꢀmodules.ꢀ
ꢀ
ꢀ
18.4 UART Control/Status Registers
18.4.1 UART Control Register
TABLE 18-2 UART Control Register
Address Name R/W
$060 UCTR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
PENꢀ
PMODꢀ UMODꢀ
BRKꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢀ
Bitꢀ3:ꢀ ꢀ PEN :ꢀParityꢀcontrolꢀbitꢀ
ꢀ=ꢀDisableꢀparityꢀ
1ꢀ=ꢀEnableꢀparityꢀ
0
ꢀ
Bitꢀ2:ꢀ ꢀ PMOD :ꢀParityꢀmodeꢀselectionꢀbitꢀ
ꢀ=ꢀEvenꢀparityꢀ
1ꢀ=ꢀOddꢀparityꢀ
0
ꢀ
Bitꢀ1:ꢀ ꢀ UMOD :ꢀ7ꢁ/8ꢁꢀbitꢀmodeꢀselectionꢀbitꢀ
ꢀ=ꢀ7ꢁꢀbitꢀmodeꢀ(theꢀreceivedꢀdataꢀbitꢀ7ꢀwillꢀbeꢀsetꢀtoꢀzero)ꢀ
1ꢀ=ꢀ8ꢁbitꢀmodeꢀ
0
ꢀ
Bitꢀ0:ꢀ ꢀ BRK :ꢀBreakꢀcharacterꢀ
ꢀ=ꢀNormalꢀcharacterꢀ
1ꢀ=ꢀTransmitꢀbreakꢀcharacterꢀ
0
ꢀ
ꢀ
18.4.2 UART Status Control Register
TABLE 18-3 UART Status Control Register
Address Name R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Rꢀ
Wꢀ
ꢁꢀ
ꢁꢀ
FERꢀ
ꢁꢀ
PERꢀ
ꢁꢀ
OERꢀ
ꢁꢀ
RXBZꢀ
RXENꢀ
TXBZꢀ
TXENꢀ ꢁ000ꢀ0000ꢀ
$061 USTR
RXTRGꢀ ꢀ RXENꢀ TXTRGꢀ TXENꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢀ
Bitꢀ6:ꢀ ꢀ FER :ꢀReceivedꢀdataꢀframeꢀerrorꢀstatusꢀbitꢀ
ꢀ=ꢀCurrentꢀreceivedꢀdataꢀisꢀnormalꢀ
1ꢀ=ꢀFrameꢀerrorꢀoccursꢀ
ꢀ
Bitꢀ3:ꢀ ꢀ RXTRG :ꢀReceiverꢀtriggerꢀbitꢀ
0
Writingꢀ“1”ꢀtoꢀmakeꢀreceiverꢀtoꢀbeꢀreadyꢀforꢀnextꢀ
dataꢀ
ꢀ
ꢀ
Bitꢀ5:ꢀ ꢀ PER :ꢀParityꢀerrorꢀstatusꢀbitꢀ
Bitꢀ1:ꢀ ꢀ TXTRG :ꢀTransmitterꢀtriggerꢀbitꢀ
Writingꢀ“1”ꢀtoꢀtriggerꢀtheꢀtransmitterꢀtoꢀstartꢀ
transmissionꢀ
0
ꢀ=ꢀCurrentꢀreceivedꢀdataꢀisꢀnormalꢀ
1ꢀ=ꢀParityꢀerrorꢀoccursꢀ
ꢀ
Bitꢀ4:ꢀ ꢀ OER :ꢀOverrunꢀerrorꢀstatusꢀbitꢀ
ꢀ=ꢀCurrentꢀreceivedꢀdataꢀisꢀnormalꢀ
1ꢀ=ꢀOverrunꢀoccursꢀ
0
ꢀ
Bitꢀ3:ꢀ ꢀ RXBZ :ꢀReceiverꢀbusyꢀbitꢀ
0
ꢀ=ꢀReceiverꢀisꢀnotꢀbusyꢀ
1ꢀ=ꢀReceiverꢀisꢀbusyꢀ
ꢀ
Bitꢀ2:ꢀ ꢀ RXEN :ꢀReceiverꢀcontrolꢀbitꢀ
0
ꢀ=ꢀReceiverꢀisꢀdisabledꢀ
1ꢀ=ꢀReceiverꢀisꢀenabledꢀ
ꢀ
Bitꢀ1:ꢀ ꢀ TXBZ :ꢀTransmitterꢀbusyꢀbitꢀ
ꢀ=ꢀTransmitterꢀisꢀnotꢀbusyꢀ
1ꢀ=ꢀTransmitterꢀisꢀbusyꢀ
0
ꢀ
Bitꢀ0:ꢀ ꢀ TXEN :ꢀTransmitterꢀcontrolꢀbitꢀ
ꢀ=ꢀTransmitterꢀisꢀdisabledꢀ
1ꢀ=ꢀTransmitterꢀisꢀenabledꢀ
0
ꢀ
Verꢀ2.5ꢀ
53
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
