ST2202A
ꢀ
POLꢀ=ꢀ0
POLꢀ=ꢀ1
OutputꢀFromꢀMaster
(MOSI)
MSB
BIT6
BIT6
BIT5
BIT5
BIT4
BIT3
BIT3
BIT2
BIT2
BIT1
BIT1
LSB
LSB
OutputꢀFromꢀSlave
(MISO)
MSB
BIT4
SS
FromꢀMaster
ꢀ
FIGURE 17-2 Transmission Format (PHA = 0)
ꢀ
ꢀ
POLꢀ=ꢀ0
POLꢀ=ꢀ1
OutputꢀFromꢀMaster
(MOSI)
MSB
MSB
BIT6
BIT6
BIT5
BIT5
BIT4
BIT4
BIT3
BIT3
BIT2
BIT2
BIT1
LSB
OutputꢀFromꢀSlave
(MISO)
BIT1
LSB
SS
FromꢀMaster
ꢀ
FIGURE 17-3 Transmission Format (PHA = 1)
ꢀ
ꢀ
17.1.2 Transmit Buffer and Receive Buffer
Operationsꢀofꢀtransmitꢀandꢀreceiveꢀbuffersꢀareꢀdiscussedꢀ
below.ꢀ
ꢀ
ꢀ
Receive Buffer
Theꢀreceiveꢀbufferꢀisꢀ16ꢁbitꢀlong,ꢀandꢀisꢀreadꢁonly.ꢀThisꢀ
bufferꢀisꢀemptyꢀafterꢀtheꢀSPIꢀwasꢀenabledꢀfirst.ꢀInꢀtheꢀ
ꢀ
Transmit Buffer
meantime,ꢀtheꢀreceiveꢀbufferꢀreadyꢀflagꢀRXRDYꢀ(SSR[6])ꢀ
willꢀbeꢀclearedꢀtoꢀindicateꢀstatusꢀofꢀbuffer.ꢀTwoꢀbytesꢀofꢀdataꢀ
canꢀbeꢀreadꢀfromꢀSDATALꢀandꢀSDATAH.ꢀAfterꢀcompletingꢀ
exchange,ꢀdataꢀinꢀshiftꢀregisterꢀwillꢀbeꢀloadedꢀintoꢀreceiveꢀ
buffer,ꢀandꢀthenꢀRXRDYꢀwillꢀbeꢀsetꢀtoꢀindicateꢀthatꢀtheꢀ
receivedꢀdataꢀisꢀavailable.ꢀNext,ꢀRXRDYꢀshouldꢀbeꢀclearedꢀ
byꢀoneꢀreadꢀinstructionꢀtoꢀSDATALꢀ(ReadingꢀSDATAHꢀwillꢀ
notꢀaffectꢀRXRDY).ꢀInꢀcaseꢀofꢀmasterꢀmode,ꢀifꢀoneꢀ
completedꢀdataꢀisꢀmovingꢀintoꢀreceiveꢀbufferꢀandꢀRXRDYꢀisꢀ
stillꢀset,ꢀtheꢀmovingꢀactivityꢀwillꢀnoꢀstopꢀbutꢀtheꢀreceiveꢀ
bufferꢀoverrunꢀflagꢀOERRꢀ(SSR[1])ꢀwillꢀbeꢀsetꢀtoꢀindicateꢀ
thatꢀanꢀoldꢀdataꢀisꢀoverwrote.ꢀIfꢀitꢀisꢀinꢀslaveꢀmode,ꢀtheꢀ
receiveꢀbufferꢀwillꢀnotꢀbeꢀoverwroteꢀwhileꢀOERRꢀequalsꢀ“1”.ꢀ
OERRꢀcanꢀbeꢀclearedꢀbyꢀreadingꢀSDATALꢀorꢀbyꢀanyꢀwriteꢀ
toꢀSSR.ꢀ
Theꢀtransmitꢀbufferꢀisꢀ16ꢁbitꢀlong,ꢀandꢀisꢀwriteꢁonly.ꢀThisꢀ
bufferꢀisꢀemptyꢀafterꢀtheꢀSPIꢀwasꢀenabledꢀatꢀtheꢀbeginning.ꢀ
Inꢀtheꢀmeantime,ꢀtheꢀtransmitꢀbufferꢀemptyꢀflagꢀTXEMP
SSR[5])ꢀwillꢀbeꢀsetꢀtoꢀindicateꢀtheꢀstatusꢀofꢀbuffer.ꢀUpꢀtoꢀ16ꢀ
bitsꢀofꢀdataꢀcanꢀbeꢀfilledꢀwithꢀwritesꢀtoꢀSPIꢀdataꢀregistersꢀ
SDATALꢀandꢀSDATAH).ꢀTXEMPꢀwillꢀbeꢀclearedꢀafterꢀ
ꢀ
(
(
SDATALꢀisꢀwroteꢀaꢀvalueꢀ(WritingꢀSDATAHꢀwillꢀnotꢀaffectꢀ
TXEMP).ꢀOnceꢀtheꢀshiftꢀregisterꢀproceedsꢀtoꢀexchange,ꢀ
dataꢀinꢀbufferꢀwillꢀbeꢀloadedꢀintoꢀshiftꢀregisterꢀandꢀTXEMP
willꢀbeꢀsetꢀagain.ꢀMeanwhileꢀaꢀSPIꢀtransmitterꢀinterruptꢀwillꢀ
beꢀissuedꢀandꢀtheꢀtransmitꢀbufferꢀcanꢀbeꢀfilledꢀwithꢀnewꢀ
dataꢀforꢀnextꢀtransmission.ꢀ
ꢀ
ꢀ
ꢀ
17.1.3 Master, Slave Modes and The Shift Register
reportedꢀatꢀMDERRꢀ(SSR[2]).ꢀ
ꢀ
TheꢀSPIꢀcanꢀoperateꢀinꢀmasterꢀorꢀslaveꢀmodeꢀaccordingꢀtoꢀ
SMODꢀ(SCTR[0]).ꢀTheseꢀtwoꢀmodesꢀandꢀoperationsꢀofꢀtheꢀ
shiftꢀregisterꢀforꢀeachꢀareꢀdiscussedꢀbelow.ꢀ
ꢀ
SomeꢀSPIꢀdevicesꢀhaveꢀ
ꢀ outputꢀtoꢀsuspendꢀ
DATA_READY
theꢀincomingꢀtransmission.ꢀSettingꢀSRDYꢀ(PFC[5])ꢀmayꢀ
includeꢀtimingꢀofꢀ ,ꢀwhileꢀclearingꢀthisꢀbitꢀtoꢀ
ꢀ
Master Mode
DATA_READY
discardꢀit.ꢀCommunicationꢀclockꢀandꢀdataꢀtransmissionꢀonlyꢀ
startsꢀafterꢀ ꢀ returnsꢀtoꢀlowꢀlevel.ꢀTheꢀactiveꢀ
TheꢀSPIꢀoperatesꢀasꢀaꢀmasterꢀdeviceꢀwhenꢀsettingꢀSMOD.ꢀ
Inꢀthisꢀmode,ꢀcommunicationꢀclockꢀisꢀprovidedꢀbyꢀST2202ꢀ
withꢀSCKꢀ(PC1).ꢀIfꢀthereꢀmayꢀhaveꢀmoreꢀthanꢀoneꢀmasterꢀ
connected,ꢀbusꢀcontentionꢀcanꢀbeꢀdetectedꢀbyꢀsettingꢀmodeꢀ
DATA_READY
ꢀ canꢀbeꢀinvertedꢀtoꢀbeꢀhighꢀlevelꢀ
levelꢀofꢀ
DATA_READY
faultꢀdetectionꢀbitꢀMERENꢀ(SCTR[4]).ꢀ
inputꢀandꢀpulledꢀhighꢀtemporarilyꢀduringꢀthisꢀdetection.ꢀ
ꢀ signalꢀshouldꢀbeꢀ
SS
activeꢀbyꢀsettingꢀinversionꢀcontrolꢀbitꢀDRINVꢀ(SCTR[3]).ꢀ
ꢀ
Whenꢀtransmission,ꢀdataꢀinꢀshiftꢀregisterꢀwillꢀbeꢀshiftedꢀtoꢀ
Onceꢀ
ꢀ inputsꢀlowꢀlevel,ꢀaꢀmodeꢀfaultꢀstatusꢀcanꢀbeꢀ
SS
Verꢀ2.5ꢀ
47
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
