ST2202A
ꢀ
ꢀ
FIGURE 18-3 IrDA ASCII “S” with Odd Parity
FIGURE 18-2 NRZ ASCII “S” with Odd Parity
ꢀ
ꢀ
PENꢀ(UCTR[3])ꢀandꢀparityꢀmodeꢀselectionꢀbitꢀPMOD
UCTR[2]).ꢀOtherꢀoperationsꢀforꢀtransmitterꢀandꢀreceiverꢀ
areꢀdescribedꢀbelow.ꢀ
ꢀ
Twoꢀkindsꢀofꢀcharacter,ꢀ7ꢁbitꢀandꢀ8ꢁbit,ꢀareꢀsupportedꢀbyꢀ
ST2202.ꢀThisꢀisꢀcontrolledꢀbyꢀmodeꢀselectionꢀbitꢀUMOD
ꢀ
(
(
UCTR[1]).ꢀParityꢀoptionsꢀareꢀcontrolledꢀbyꢀparityꢀenableꢀbitꢀ
ꢀ
18.2.3 Transmitter Operation
TransmitterꢀoperationꢀisꢀcontrolledꢀbyꢀcontrolꢀbitꢀTXEN
ꢀ
finished,ꢀIRUTXꢀ(IREQ[10])ꢀwillꢀbeꢀsetꢀtoꢀissueꢀtheꢀinterruptꢀ
request.ꢀNextꢀdataꢀtransmissionꢀmayꢀcontinueꢀwithꢀsettingꢀ
triggerꢀbitꢀTXTRGꢀagain.ꢀ
(
USTR[0]).ꢀTheꢀtransmitterꢀacceptsꢀaꢀcharacterꢀfromꢀtheꢀ
CPUꢀbus,ꢀandꢀthenꢀtransmitsꢀitꢀimmediatelyꢀafterꢀtriggeredꢀ
byꢀwritingꢀ“1”ꢀtoꢀcontrolꢀbitꢀTXTRGꢀ(USTR[1]).ꢀWhenꢀaꢀ
characterꢀisꢀavailableꢀforꢀtransmission,ꢀtheꢀstart,ꢀstop,ꢀandꢀ
parityꢀ(ifꢀenabled)ꢀbitsꢀareꢀaddedꢀintoꢀtheꢀcharacter,ꢀandꢀ
thenꢀitꢀisꢀseriallyꢀshiftedꢀ(LSBꢀfirst)ꢀatꢀtheꢀselectedꢀbitꢀrate.ꢀ
Whileꢀtransmitterꢀisꢀbusy,ꢀtheꢀbusyꢀstatusꢀisꢀreportedꢀatꢀ
TXBZꢀ(USTR[1])ꢀwithꢀlogicꢀvalueꢀ“1”.ꢀAfterꢀallꢀdataꢀbitsꢀareꢀ
ꢀ
ꢀ
Ifꢀtheꢀtransmitꢀbufferꢀisꢀempty,ꢀtheꢀtransmitterꢀoutputsꢀaꢀ
continuousꢀidleꢀ(whichꢀisꢀ“1”ꢀforꢀnormalꢀpolarity).ꢀMoreoverꢀ
aꢀcontinuousꢀ“0”ꢀcanꢀalsoꢀbeꢀoutputtedꢀasꢀaꢀbreakꢀcharacterꢀ
byꢀsettingꢀBRKꢀbitꢀ(UCTR[0])ꢀandꢀthenꢀsetꢀtheꢀtriggerꢀbit.ꢀ
.
ꢀ
18.2.4 Receiver Operation
ReceiverꢀoperationꢀisꢀcontrolledꢀbyꢀcontrolꢀbitꢀRXEN
ꢀ
1. Buffer Overrun Error
(
USTR[2]).ꢀOnceꢀtheꢀreceiverꢀisꢀenabled,ꢀitꢀsearchesꢀforꢀaꢀ
Thisꢀerrorꢀindicatesꢀthatꢀtheꢀreceiveꢀtriggerꢀbitꢀwasꢀnotꢀsetꢀ
andꢀtheꢀreceiverꢀoverwroteꢀdataꢀinꢀreceiveꢀbuffer,ꢀi.e.,ꢀtheꢀ
previousꢀcharacterꢀwasꢀlost.ꢀThisꢀalsoꢀmeansꢀtheꢀsoftwareꢀ
isꢀnotꢀkeepingꢀupꢀwithꢀtheꢀincomingꢀdataꢀrate.ꢀErrorꢀisꢀ
updatedꢀandꢀreportedꢀbyꢀreadingꢀOERꢀ(USTR[4])ꢀforꢀ
currentꢀreceivedꢀcharacter.ꢀ
startꢀbit,ꢀqualifiesꢀit,ꢀandꢀthenꢀsamplesꢀtheꢀsucceedingꢀdataꢀ
bitsꢀatꢀtheꢀperceivedꢀbitꢀcenter.ꢀJitterꢀtoleranceꢀandꢀnoiseꢀ
immunityꢀareꢀprovidedꢀbyꢀsamplingꢀ16ꢀtimesꢀperꢀbitꢀandꢀ
usingꢀaꢀvotingꢀcircuitꢀtoꢀenhanceꢀsampling.ꢀWhileꢀreceiving,ꢀ
theꢀbusyꢀstatusꢀofꢀreceiverꢀcanꢀbeꢀreadꢀfromꢀRXBZ
ꢀ
(
ꢀ
USTR[3])ꢀwithꢀlogicꢀlevelꢀ“1”.ꢀ
ꢀ
2. Parity Error
Receivingꢀactivityꢀwillꢀbeꢀcompleteꢀafterꢀtheꢀstopꢀbitꢀisꢀ
detected.ꢀThenꢀIRURXꢀ(IREQ[11])ꢀwillꢀbeꢀsetꢀtoꢀissueꢀtheꢀ
interruptꢀrequest.ꢀTheꢀreceivedꢀdataꢀcanꢀbeꢀobtainedꢀbyꢀ
readingꢀdataꢀregisterꢀUDATA.ꢀThenꢀtheꢀreceiveꢀtriggerꢀbitꢀ
RXTRGꢀ(USTR[3])ꢀshouldꢀbeꢀsetꢀtoꢀindicateꢀthatꢀtheꢀdataꢀ
registerꢀcanꢀbeꢀoverwroteꢀnextꢀtime.ꢀ
Ifꢀparityꢀisꢀenabled,ꢀtheꢀparityꢀbitꢀofꢀcurrentꢀreceivedꢀ
characterꢀisꢀcheckedꢀandꢀtheꢀstatusꢀisꢀupdatedꢀinꢀregisterꢀ
bitꢀPERꢀ(USTR[5]).ꢀ
ꢀ
3. Framing Error
Thisꢀerrorꢀindicatesꢀthatꢀaꢀframingꢀerrorꢀisꢀdetectedꢀandꢀ
thereꢀmayꢀbeꢀcorruptedꢀdataꢀwithꢀmissingꢀstopꢀbit.ꢀErrorꢀisꢀ
updatedꢀandꢀreportedꢀbyꢀreadingꢀFERꢀ(USTR[6])ꢀforꢀcurrentꢀ
receivedꢀcharacter.
ꢀ
Threeꢀkindsꢀofꢀerrorsꢀmayꢀariseꢀfromꢀillegalꢀreceivedꢀdata,ꢀ
whichꢀareꢀreportedꢀatꢀ3ꢀbitsꢀofꢀstatusꢀregisterꢀUSTR[6:4]
ꢀ
andꢀareꢀdiscussedꢀbelow.ꢀ
ꢀ
ꢀ
18.3 Interface Signals
Twoꢀsetsꢀofꢀdataꢀlinesꢀcanꢀbeꢀenabledꢀsimultaneouslyꢀforꢀ
communication,ꢀTXD0(PC6),ꢀRXD0(PC7)ꢀandꢀtheꢀauxiliaryꢀ
pinsꢀTXD1(PD6),ꢀRXD1(PD7).ꢀDataꢀcanꢀinputsꢀandꢀoutputsꢀ
fromꢀandꢀtoꢀtheseꢀpins.ꢀWithꢀsettingꢀrelatedꢀbitsꢀofꢀportꢀ
functionꢀselectꢀregistersꢀ(PFCꢀandꢀPFD),ꢀsignalsꢀofꢀtheꢀ
externalꢀdevicesꢀcanꢀbeꢀconnected.ꢀDataꢀinꢀandꢀfromꢀtheseꢀ
communicationꢀI/Osꢀcanꢀbeꢀinvertedꢀbyꢀsettingꢀpolarityꢀ
controlꢀbitꢀRXINVꢀandꢀTXINVꢀ(IRCTR[7:6]).ꢀDirectionꢀ
settingsꢀandꢀfunctionꢀselectꢀbitsꢀshouldꢀbeꢀascertainedꢀ
beforeꢀusingꢀsignals.ꢀReferꢀtoꢀsectionꢀ9ꢀforꢀtheseꢀsettings.ꢀ
ꢀ
ꢀ
TXD0 (PC6)/TXD1 (PD6)
TheꢀUARTꢀtransmitꢀdataꢀsignalꢀisꢀoutputꢀtoꢀoneꢀorꢀbothꢀofꢀ
theseꢀtwoꢀpins,ꢀwhichꢀareꢀmultiplexedꢀwithꢀPC6ꢀandꢀPD6.ꢀ
TheseꢀpinsꢀconnectꢀtoꢀstandardꢀRSꢁ232ꢀorꢀinfraredꢀ
transceiverꢀmodules.ꢀ
ꢀ
ꢀ
TheꢀUARTꢀreceiveꢀdataꢀsignalꢀisꢀinputꢀfromꢀoneꢀorꢀbothꢀofꢀ
theseꢀtwoꢀpins,ꢀwhichꢀareꢀmultiplexedꢀwithꢀPC7ꢀandꢀPD7.ꢀIfꢀ
RXD0ꢀandꢀRXD1ꢀareꢀenabledꢀatꢀaꢀtime,ꢀbothꢀsignalsꢀwillꢀbeꢀ
gatedꢀwithꢀANDꢀlogicꢀtoꢀproduceꢀoneꢀsingleꢀsignal.ꢀTheseꢀ
RXD0 (PC7)/RXD1 (PD7)
Verꢀ2.5ꢀ
52
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
