ST2202A
masterꢀdataꢀoutputꢀMOSIꢀ(PC3)ꢀwithꢀmostꢀsignificantꢀbitꢀ
(MSB)ꢀfirst,ꢀwhileꢀdataꢀfromꢀserialꢀdataꢀinputꢀMISOꢀ(PC2)ꢀ
willꢀbeꢀshiftedꢀinꢀasꢀwell.ꢀAfterꢀtheꢀexchangedꢀbitsꢀreachꢀbitꢀ
countꢀsetting,ꢀcurrentꢀdataꢀisꢀcompleteꢀandꢀthenꢀmovesꢀtoꢀ
receiveꢀbuffer.ꢀ
ꢀ
Slave Mode
Inꢀslaveꢀmode,ꢀ
ꢀ (PC5)ꢀandꢀSCKꢀ(PC1)ꢀbecomeꢀinput,ꢀ
SS
whileꢀ
ꢀ (PC5)ꢀisꢀnotꢀfunctional.ꢀTheꢀexchangeꢀ
DATA_READY
takesꢀplaceꢀonlyꢀwhenꢀ
ꢀ inputsꢀlowꢀlevelꢀandꢀendsꢀwhenꢀ
SS
ꢀ
itꢀreturnsꢀtoꢀhigh.ꢀOnꢀtheꢀfallingꢀedgeꢀofꢀ
,ꢀtheꢀshiftꢀ
SS
Theꢀexchangeꢀcontinuesꢀwithꢀautoꢀreloadꢀfunctionꢀofꢀshiftꢀ
registerꢀifꢀTXEMPꢀisꢀcleared.ꢀThatꢀis,ꢀMSBꢀofꢀnextꢀdataꢀwillꢀ
beꢀsentꢀoutꢀandꢀbeꢀreceivedꢀinꢀrightꢀafterꢀtheꢀLSBꢀofꢀtheꢀ
previousꢀoneꢀwithꢀnoꢀpause.ꢀ
registerꢀwillꢀbeꢀloadedꢀwithꢀdataꢀinꢀtransmitꢀbuffer,ꢀandꢀthenꢀ
theꢀexchangeꢀinitiates.ꢀDuringꢀexchanging,ꢀdataꢀisꢀclockedꢀ
byꢀexternalꢀclockꢀfromꢀSCKꢀandꢀisꢀshiftedꢀinꢀandꢀoutꢀtheꢀ
shiftꢀregister.ꢀExchangedꢀdataꢀwillꢀbeꢀreadyꢀwhenꢀtheꢀ
exchangedꢀbitꢀnumberꢀmatchesꢀbitꢀcountꢀsetting.ꢀAfterꢀdataꢀ
isꢀready,ꢀdataꢀtransferꢀbetweenꢀshiftꢀregisterꢀandꢀtwoꢀbuffersꢀ
willꢀfunctionꢀautomaticallyꢀasꢀitꢀdoesꢀinꢀmasterꢀmode.ꢀSoꢀ
thatꢀtheꢀshiftꢀregisterꢀcanꢀbeꢀreadyꢀforꢀtheꢀsucceedingꢀclockꢀ
ꢀ
Afterꢀtheꢀexchangeꢀwasꢀtriggered,ꢀtheꢀslaveꢁselectꢀsignalꢀ
ꢀ (PC4)ꢀoutputsꢀlowꢀlevelꢀtoꢀenableꢀtheꢀexternalꢀslaveꢀ
SS
device.ꢀItꢀkeepsꢀatꢀlowꢀlevelꢀduringꢀexchangesꢀofꢀdataꢀandꢀ
data,ꢀandꢀreturnsꢀtoꢀhighꢀwhenꢀexchangesꢀcease.ꢀ
ꢀ
edge.ꢀIfꢀ
ꢀ risesꢀbeforeꢀenoughꢀdataꢀbits,ꢀcurrentꢀ
SS
exchangeꢀisꢀoverꢀanyway,ꢀbutꢀtheꢀbitꢀcountꢀviolationꢀflagꢀ
BERRꢀ(SSR[0])ꢀwillꢀbeꢀset.ꢀ
ꢀ
ꢀ
17.1.4 SPI Interrupts
FourꢀinterruptsꢀareꢀsupportedꢀbyꢀSPIꢀwithꢀtwoꢀinterruptꢀ
vectors.ꢀ
ꢀ
interruptꢀvectorꢀwithꢀreceiveꢀbufferꢀreadyꢀinterrupt.ꢀTheseꢀ
threeꢀinterruptsꢀareꢀ“OR”ꢀtogetherꢀtoꢀgenerateꢀanꢀindividualꢀ
vector.ꢀInꢀmasterꢀmode,ꢀreceiveꢀbufferꢀoverrunꢀinterruptꢀ
happensꢀwhenꢀmovingꢀnewꢀdataꢀfromꢀshiftꢀregisterꢀtoꢀ
receiveꢀbufferꢀwithꢀRXRDYꢀequalsꢀ“1”.ꢀTheꢀoverrunꢀinterruptꢀ
isꢀissuedꢀandꢀtheꢀstatusꢀbitꢀOERRꢀ(SSR[1])ꢀwillꢀbeꢀset.ꢀInꢀ
slaveꢀmode,ꢀoldꢀdataꢀinꢀreceiveꢀbufferꢀwillꢀnotꢀbeꢀflushedꢀ
whileꢀotherꢀoperationsꢀareꢀtheꢀsameꢀwithꢀthoseꢀinꢀmasterꢀ
mode.ꢀ
Transmitꢀbufferꢀemptyꢀinterruptꢀhappensꢀwhenꢀaꢀdataꢀ
exchangeꢀstartsꢀandꢀtheꢀtransmitꢀbufferꢀisꢀempty.ꢀThisꢀ
statusꢀcanꢀbeꢀreadꢀfromꢀstatusꢀbitꢀTXEMPꢀ(SSR[5]).ꢀ
ꢀ
Receiveꢀbufferꢀreadyꢀinterruptꢀhappensꢀwhenꢀaꢀdataꢀ
exchangeꢀcompletesꢀandꢀtheꢀreceiveꢀbufferꢀisꢀfilledꢀwithꢀoneꢀ
newꢀdata.ꢀThisꢀinterruptꢀisꢀenabledꢀbyꢀsettingꢀcontrolꢀbitꢀ
RXIENꢀ(SCTR[6]).ꢀTheꢀstatusꢀisꢀreportedꢀatꢀstatusꢀbitꢀ
RXRDYꢀ(SSR[6]).ꢀ
ꢀ
Bitꢀcountꢀviolationꢀinterruptꢀonlyꢀhappensꢀinꢀslaveꢀmode.ꢀIfꢀ
ꢀ inputꢀrisesꢀbeforeꢀenoughꢀdataꢀbitsꢀareꢀreached,ꢀ
SS
ꢀ
currentꢀexchangeꢀisꢀoverꢀanyway,ꢀbutꢀtheꢀbitꢀcountꢀviolationꢀ
flagꢀBERRꢀ(SSR[0])ꢀwillꢀbeꢀsetꢀandꢀtheꢀinterruptꢀisꢀissued.
Theꢀotherꢀtwoꢀinterruptsꢀareꢀerrorꢀinterruptsꢀandꢀareꢀbothꢀ
enabledꢀbyꢀcontrolꢀbitꢀERIENꢀ(SCTR[5]).ꢀReceiveꢀbufferꢀ
overrunꢀinterruptꢀandꢀbitꢀcountꢀviolationꢀinterruptꢀshareꢀtheꢀ
ꢀ
ꢀ
17.2 Interface Signals
FiveꢀmultiplexedꢀsignalsꢀareꢀusedꢀtoꢀinterfaceꢀwithꢀotherꢀSPIꢀ
devices.ꢀWithꢀsettingꢀrelatedꢀbitsꢀofꢀportꢀfunctionꢀselectꢀ
registerꢀPFC,ꢀtheseꢀsignalsꢀcanꢀbeꢀactivated.ꢀDirectionꢀandꢀ
functionꢀselectꢀbitsꢀshouldꢀbeꢀascertainedꢀbeforeꢀtheyꢀareꢀ
used.ꢀReferꢀtoꢀsectionꢀ9ꢀforꢀtheseꢀsettings.ꢀ
ꢀ
ꢀ
ꢀ
(PC4)
SS
ꢀ isꢀaꢀbidirectionalꢀslaveꢁselectꢀsignal,ꢀwhichꢀisꢀ
SS
multiplexedꢀwithꢀPC4.ꢀInꢀmasterꢀmode,ꢀ
ꢀ isꢀoutputꢀtoꢀ
SS
ꢀ isꢀinputtedꢀaꢀlowꢀ
enableꢀaꢀslaveꢀdevice.ꢀInꢀslaveꢀmode,ꢀ
levelꢀtoꢀtriggerꢀtheꢀexchange.ꢀ
ꢀ
SS
ꢀ
SCK (PC1)
ThisꢀisꢀaꢀbidirectionalꢀSPIꢀsynchronousꢀclockꢀI/O,ꢀwhichꢀisꢀ
multiplexedꢀwithꢀPC1.ꢀSCKꢀisꢀoutputꢀinꢀmasterꢀmodeꢀandꢀ
inputꢀinꢀslaveꢀmode.ꢀ
ꢀ
ꢀ
(PC5)
DATA_READY
isꢀanꢀinputꢀsignal,ꢀwhichꢀisꢀmultiplexedꢀwithꢀ
DATA_READY
ꢀ
MISO (PC2)
PC5.ꢀItꢀisꢀusedꢀonlyꢀinꢀmasterꢀmodeꢀandꢀcanꢀbeꢀaꢀGPIOꢀinꢀ
slaveꢀmode.ꢀTheꢀoperationꢀofꢀ ꢀ canꢀbeꢀ
enabledꢀbyꢀsettingꢀPFC[5].ꢀTheꢀdefaultꢀactiveꢀlevelꢀisꢀhigh,ꢀ
andꢀcanꢀbeꢀinvertedꢀbyꢀsettingꢀDRINVꢀ(SCTR[3]).ꢀActiveꢀ
levelꢀisꢀinputtedꢀtoꢀindicateꢀthatꢀtheꢀcommunicatingꢀslaveꢀisꢀ
readyꢀforꢀdataꢀexchange.ꢀ
ꢀ
ꢀ
MasterꢀIn/SlaveꢀOutꢀbidirectionalꢀsignal,ꢀwhichꢀisꢀ
multiplexedꢀwithꢀPC2.ꢀExternalꢀdataꢀisꢀinputtedꢀtoꢀthisꢀpinꢀtoꢀ
theꢀshiftꢀregisterꢀinꢀmasterꢀmode.ꢀInꢀslaveꢀmode,ꢀitꢀisꢀanꢀ
outputꢀofꢀshiftꢀregister.ꢀ
ꢀ
ꢀ
MasterꢀOut/SlaveꢀInꢀbidirectionalꢀsignal,ꢀwhichꢀisꢀ
multiplexedꢀwithꢀPC3.ꢀDataꢀinꢀshiftꢀregisterꢀisꢀoutputtedꢀfromꢀ
thisꢀpinꢀinꢀmasterꢀmode.ꢀInꢀslaveꢀmode,ꢀitꢀisꢀanꢀinputꢀofꢀ
externalꢀdataꢀtoꢀtheꢀshiftꢀregister.ꢀ
DATA_READY
MOSI (PC3)
Verꢀ2.5ꢀ
48
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
