ST2202A
17.3.3 SPI Status Register
TABLE 17-5 SPI Status Register
Address Name R/W
Bit 7
ꢁꢀ
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Rꢀ
RXRDYꢀ TXEMPꢀ
SBZꢀ
ꢁꢀ
MDERRꢀ OERRꢀ BCERRꢀ ꢁ000ꢀꢁ000ꢀ
$054 SSR
WriteꢀanyꢀvalueꢀtoꢀresetꢀSSR
ꢀ
Wꢀ
ꢀ
ꢀ
Bitꢀ6:ꢀ ꢀ RXRDYꢀ:ꢀReceiveꢀbufferꢀstatusꢀflagꢀ
0
ꢀ=ꢀReceiveꢀbufferꢀisꢀemptyꢀ
1ꢀ=ꢀReceiveꢀbufferꢀisꢀfilledꢀwithꢀnewꢀdataꢀandꢀisꢀreadyꢀ
ꢀ
Bitꢀ5:ꢀ ꢀ TXEMP
ꢀ:ꢀTransmitꢀbufferꢀstatusꢀflagꢀ
0
ꢀ=ꢀDataꢀinꢀtransmitꢀbufferꢀisꢀwaitingꢀforꢀexchangingꢀ
1ꢀ=ꢀTransmitꢀbufferꢀisꢀemptyꢀ
ꢀ
Bitꢀ4:ꢀ ꢀ SBZ
ꢀ=ꢀSPIꢀisꢀidleꢀ ꢀ
1ꢀ=ꢀSPIꢀisꢀbusyꢀexchangingꢀdataꢀ
ꢀ:ꢀSPIꢀbusyꢀflagꢀ
0
ꢀ
Bitꢀ2:ꢀ ꢀ MDERR :ꢀModeꢀfaultꢀstatusꢀflagꢀ
0
ꢀ=ꢀ
ꢀ signalꢀisꢀatꢀhighꢀlevelꢀandꢀisꢀnormalꢀ
SS
SS
1ꢀ=ꢀ
ꢀ
ꢀ signalꢀinputsꢀlowꢀlevelꢀ/ꢀaꢀmodeꢀfaultꢀstatusꢀdetectedꢀ
Bitꢀ1:ꢀ ꢀ OERR :ꢀReceiveꢀbufferꢀoverrunꢀerrorꢀflagꢀ
ꢀ=ꢀNoꢀreceiveꢀbufferꢀoverrunꢀerrorꢀ
0
1ꢀ=ꢀReceiveꢀbufferꢀoverrunꢀerrorꢀoccursꢀ
ꢀ
Bitꢀ0:ꢀ ꢀ BERR :ꢀBitꢀcountꢀviolationꢀflagꢀ
0
ꢀ=ꢀExchangedꢀdataꢀbitꢀnumberꢀmatchesꢀbitꢀcountꢀsettingꢀinꢀslaveꢀmodeꢀ
1ꢀ=ꢀExchangedꢀdataꢀbitꢀnumberꢀisꢀlessꢀthanꢀbitꢀcountꢀsettingꢀinꢀslaveꢀmodeꢀ
Verꢀ2.5ꢀ
50
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
