ST2202A
17. SERIAL PERIPHERAL INTERFACE
TheꢀST2202ꢀcontainsꢀoneꢀserialꢀperipheralꢀinterfaceꢀ(SPI)ꢀ
moduleꢀtoꢀinterfaceꢀwithꢀexternalꢀdevices,ꢀsuchꢀasꢀFlashꢀ
memory,ꢀanalogꢁtoꢁdigitalꢀconverter,ꢀandꢀotherꢀperipherals,ꢀ
includingꢀanotherꢀST2202.ꢀTheꢀSPIꢀconsistsꢀofꢀaꢀmasterꢁꢀorꢀ
slaveꢁconfigurableꢀinterfaceꢀsoꢀthatꢀconnectionsꢀofꢀbothꢀ
masterꢀandꢀslaveꢀdevicesꢀareꢀallowable.ꢀFiveꢀsignalsꢀ
multiplexedꢀwithꢀPortꢁCꢀareꢀusedꢀbyꢀSPI.ꢀWithꢀequippedꢀ
transmit/receiveꢀbuffers,ꢀfasterꢀdataꢀexchangeꢀwithꢀfewerꢀ
softwareꢀinterruptsꢀisꢀeasyꢀtoꢀbeꢀmade.ꢀDataꢀlengthꢀisꢀ
widelyꢀsupportedꢀfromꢀ7ꢁbitꢀupꢀtoꢀ16ꢁbitꢀtoꢀsatisfyꢀvariousꢀ
applications.ꢀOneꢀclockꢀgeneratorꢀisꢀprovidedꢀforꢀtheꢀ
synchronousꢀcommunicationꢀclockꢀSCK,ꢀwhichꢀisꢀsourcedꢀ
fromꢀOSCK.ꢀFIGUREꢀ17ꢁ1ꢀillustratesꢀtheꢀblockꢀdiagramꢀofꢀ
SPI.ꢀ
ꢀ andꢀ
ꢀ (slaveꢁselect)ꢀcontrolꢀsignalsꢀandꢀ
DATA_READY
SS
ꢀ
DATA_READY
CPUꢀInterface
SS
Interface
Control
SCK
16ꢁbitꢀReceive 16ꢁbitꢀTransmit
OSCK
Clock
Buffer
Buffer
SPICK
Generator
MISO
MOSI
16ꢁbitꢀShiftꢀRegister
(MSBꢀFirst)
ꢀ
FIGURE 17-1 SPI Block Diagram
ꢀ
17.1 SPI Operations
TheꢀSPIꢀblockꢀisꢀcontrolledꢀbyꢀSPIENꢀ(SCTR[7]).ꢀSettingꢀ
SPIENꢀwillꢀenableꢀSPIꢀfunctionꢀandꢀtheꢀclockꢀdivider.ꢀThenꢀ
theꢀinternalꢀstatesꢀofꢀSPIꢀwillꢀbeꢀresetꢀtoꢀinitialꢀvalues.ꢀAfterꢀ
that,ꢀwriteꢀdataꢀtoꢀSDATALꢀwillꢀinitiateꢀanꢀexchange.ꢀWhileꢀ
exchanging,ꢀtheꢀbusyꢀflagꢀwillꢀbeꢀsetꢀandꢀisꢀreportedꢀinꢀSBZ
(bitꢀ4ꢀofꢀSPIꢀstatusꢀregisterꢀSSR).ꢀ ꢀ
TheꢀSPIꢀcontainsꢀoneꢀ16ꢁbitꢀshiftꢀregisterꢀandꢀtwoꢀ16ꢁbitꢀ
buffersꢀforꢀtransmissionꢀandꢀreceivingꢀrespectively.ꢀDataꢀ
withꢀvariableꢀlengthꢀfromꢀ7ꢁbitꢀtoꢀ16ꢁbitꢀcanꢀbeꢀexchangedꢀ
withꢀexternalꢀdevicesꢀthroughꢀtwoꢀdataꢀlines.ꢀDataꢀlengthꢀisꢀ
controlledꢀbyꢀbitꢀcountꢀregisterꢀBC[3:0]ꢀ(bit3~0ꢀofꢀSPIꢀclockꢀ
controlꢀregisterꢀSCKR).ꢀTheꢀcurrentꢀexchangeꢀwillꢀbeꢀoverꢀ
whileꢀtheꢀexchangedꢀbitꢀnumberꢀreachesꢀbitꢀcountꢀsetting.ꢀ
ꢀ
ꢀ
ꢀ
Aꢀslaveꢀselectꢀsignalꢀ
ꢀ (multiplexedꢀwithꢀPC4)ꢀisꢀusedꢀtoꢀ
SS
TheꢀsynchronousꢀcommunicationꢀclockꢀSCKꢀisꢀusedꢀtoꢀ
synchronizeꢀtwoꢀdevicesꢀandꢀtransferꢀdataꢀinꢀandꢀoutꢀofꢀtheꢀ
shiftꢀregister.ꢀDataꢀisꢀclockedꢀbyꢀSCKꢀwithꢀaꢀprogrammableꢀ
dataꢀrate,ꢀwhichꢀisꢀassignedꢀbyꢀSCK[2:0]ꢀ(bit6~4ꢀofꢀSPIꢀ
clockꢀcontrolꢀregisterꢀSCKR).ꢀReferꢀtoꢀTABLEꢀ11ꢁ7ꢀforꢀallꢀ
clockꢀrateꢀsettings.ꢀ
identifyꢀindividualꢀselectionꢀofꢀaꢀslaveꢀSPIꢀdevice.ꢀSlaveꢀ
devicesꢀthatꢀareꢀnotꢀselectedꢀdoꢀnotꢀinterfereꢀwithꢀSPIꢀbusꢀ
activities.ꢀForꢀaꢀmasterꢀSPIꢀdevice,ꢀ
ꢀ canꢀbeꢀusedꢀtoꢀ
SS
indicateꢀaꢀmultipleꢁmasterꢀbusꢀcontentionꢀwhichꢀcanꢀbeꢀ
reportedꢀinꢀmodeꢀfaultꢀbitꢀMDERRꢀ(bit3ꢀofꢀSPIꢀstatusꢀ
registerꢀSSR).ꢀ
ꢀ
ꢀ
17.1.1 Clock Phase and Polarity Controls
Fourꢀcombinationsꢀofꢀserialꢀclockꢀ(SCK)ꢀphaseꢀandꢀpolarityꢀ
areꢀselectableꢀbyꢀtwoꢀcontrolꢀbitsꢀPHAꢀandꢀPOLꢀ(bitꢀ2~1ꢀofꢀ
SPIꢀcontrolꢀregisterꢀSCTR).ꢀFIGUREꢀ17ꢁ2ꢀandꢀFIGUREꢀ
17ꢁ3ꢀshowꢀtheꢀtransmissionꢀformatꢀofꢀtwoꢀphaseꢀsettings.ꢀ ꢀ
ꢀ
Theꢀclockꢀsettingsꢀshouldꢀbeꢀidenticalꢀforꢀ
masterꢀandꢀtheꢀcommunicatingꢀslaveꢀdevice.ꢀ ꢀ
ꢀ
Note:ꢀ
ꢀ
Transmission Format – PHA = 0
Inꢀthisꢀmode,ꢀbothꢀmasterꢀandꢀtheꢀcommunicatingꢀslaveꢀ
shouldꢀpresentꢀMSBꢀafterꢀtheꢀfallingꢀedgeꢀofꢀ .ꢀThenꢀtheꢀ
ꢀ
Transmission Format – PHA = 1
Inꢀthisꢀmode,ꢀbothꢀmasterꢀandꢀtheꢀcommunicatingꢀslaveꢀwillꢀ
beꢀreadyꢀafterꢀtheꢀfallingꢀedgeꢀofꢀ .ꢀTheꢀtwoꢀoutputꢀMSBꢀ
SS
SS
firstꢀedgeꢀofꢀSCKꢀwillꢀbeꢀtheꢀfirstꢀcaptureꢀstrobeꢀofꢀinputꢀ
data.ꢀIfꢀPOL=0,ꢀthisꢀfirstꢀedgeꢀisꢀrisingꢀedge;ꢀifꢀPOL=1,ꢀitꢀwillꢀ
beꢀaꢀfallingꢀedge.ꢀ
ꢀ
atꢀtheꢀfirstꢀedgeꢀofꢀSCK.ꢀThenꢀtheꢀsecondꢀedgeꢀwillꢀbeꢀtheꢀ
captureꢀstrobe.ꢀIfꢀPOL=0,ꢀtheꢀfirstꢀedgeꢀisꢀrisingꢀedge;ꢀifꢀ
POL=1,ꢀitꢀwillꢀbeꢀaꢀfallingꢀone.ꢀ
ꢀ
Verꢀ2.5ꢀ
46
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ꢀ
9/16/2008ꢀ
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