SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.26 System Software Data Register
Address Offset: 8CH
Access Type: Read/Write
Reset Value: Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
System Software Data
This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are never
cleared by any type of reset. The register bits are also mapped to Base Address 5, Offset 4CH. See Section 9.7.14 for bit
definitions.
9.1.27 FLASH Memory Address – Command + Status
Address Offset: 90H
Access Type: Read/Write
Reset Value: 0x0000_0000
This register defines the address and command/status register for FLASH memory interface in the SiI 0680A. The register bits
are also mapped to Base Address 5, Offset 50H. See Section 9.7.15 for bit definitions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Memory Address
9.1.28 FLASH Memory Data
Address Offset: 94H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Memory Data
This register defines the data register for FLASH memory interface in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset 54H. See Section 9.7.16 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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