SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.23 Data Transfer Mode – IDE0
Address Offset: 80H
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the transfer mode register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset B4H. See Section 9.7.38 for bit definitions.
9.1.24 Data Transfer Mode – IDE1
Address Offset: 84H
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the transfer mode register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset F4H. See Section 9.7.52 for bit definitions.
9.1.25 System Configuration Status – Command
Address Offset: 88H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Reserved
This register defines the system configuration status and command register for the SiI 0680A. The register bits are also
mapped to Base Address 5, Offset 48H. See Section 9.7.13 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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