SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.20 PRD Table Address – IDE0
Address Offset: 74H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE0
This register defines the PRD Table Address register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped
to Base Address 4, Offset 04H and Base Address 5, Offset 04H. See Section 9.7.2 for bit definitions.
9.1.21 PCI Bus Master – IDE1
Address Offset: 78H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Reserved
This register defines the PCI bus master register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to
Base Address 4, Offset 08H, Base Address 5, Offset 08H, and Base Address 5, Offset 18H. See Section 9.7.3 for bit
definitions.
9.1.22 PRD Table Address – IDE1
Address Offset: 7CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE1
This register defines the PRD Table Address register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped
to Base Address 4, Offset 0CH and Base Address 5, Offset 0CH. See Section 9.7.4 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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