SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
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Bit [19]: PME Clock (R) – Power Management Event Clock. This bit is hardwired to 0. The SiI 0680A does not
support PME.
Bit [18:16]: PPM Rev (R) – PCI Power Management Revision. This bit field is hardwired to 010B to indicate
compliance with the PCI Power Management Interface Specification revision 1.1.
Bit [15:08]: Next Item Pointer (R) – PCI Additional Capability Next Item Pointer. This bit field is hardwired to 00H
to indicate that there are no additional items on the Capabilities List.
Bit [07:00]: Capability ID (R) – PCI Additional Capability ID. This bit field is hardwired to 01H to indicate that this
Capabilities List is a PCI Power Management definition.
9.1.18 Power Management Control + Status
Address Offset: 64H
Access Type: Read/Write
Reset Value: 0x6400_4000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PPM Data
Reserved
PPM Data Sel
Reserved
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
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Bit [31:24]: PPM Data (R) – PCI Power Management Data. This bit field is hardwired to 64h.
Bit [23:16]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15]: PME Status (R) – PME Status. This bit field is hardwired to 0. The SiI 0680A does not support PME.
Bit [14:13]: PPM Data Scale (R) – PCI Power Management Data Scale. This bit field is hardwired to 11B to
indicate a scaling factor of one.
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Bit [12:09]: PPM Data Sel (R/W) – PCI Power Management Data Select. This bit field is set by the system to
indicate which data field is to be reported through the PPM Data bits.
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Bit [08]: PME Ena (R) – PME Enable. This bit field is hardwired to 0. The SiI 0680A does not support PME.
Bit [07:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]: PPM Power State (R/W) – PCI Power Management Power State. This bit field is set by the system
to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3 Hot.
9.1.19 PCI Bus Master – IDE0
Address Offset: 70H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Reserved
This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to
Base Address 4, Offset 00H, Base Address 5, Offset 00H, and Base Address 5, Offset 10H. See Section 9.7.1 for bit
definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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