SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.32 IDE0 PIO Timing
Address Offset: A4H
Access Type: Read/Write
Reset Value: 0x62DD_62DD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device 1 Addr
Setup Count
Device 1 Active Count
Device 1 Recovery
Count
Device 0 Addr
Setup Count
Device 0 Active Count
Device 0 Recovery
Count
This register defines the PIO timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset A4H. See Section 9.7.34 for bit definitions.
9.1.33 IDE0 DMA Timing
Address Offset: A8H
Access Type: Read/Write
Reset Value: 0x4392_4392
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device 1 Addr
Setup Count
Device 1 Active Count
Device 1 Recovery
Count
Device 0 Addr
Setup Count
Device 0 Active Count
Device 0 Recovery
Count
This register defines the DMA timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset A8H. See Section 9.7.35 for bit definitions.
9.1.34 IDE0 UDMA Timing
Address Offset: ACH
Access Type: Read/Write
Reset Value: 0x4009_4009
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device 1 Cycle Time
Count
Device 0 Cycle Time
Count
This register defines the UDMA timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset ACH. See Section 9.7.36 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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