SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.15 Configuration
Address Offset: 40H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
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Bit [31:01]: Reserved (R). This bit field is hardwired to 00000000H.
Bit [00]: PCI Hdr Wr Ena (R/W) – PCI Configuration Header Write Enable. This bit is set to enable write access
to the following registers in the PCI Configuration Header: Device ID (03-02H), PCI Class Code (09-0BH),
Subsystem Vendor ID (2D-2CH), and Subsystem ID (2F-2EH).
9.1.16 Software Data Register
Address Offset: 44H
Access Type: Read/Write
Reset Value: Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Software Data
This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are never
cleared by any type of reset.
9.1.17 Power Management Capabilities
Address Offset: 60H
Access Type: Read Only
Reset Value: 0x0622_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PME Support
Auxiliary
Current
PPM Rev
Next Item Pointer
Capability ID
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
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Bit [31:27]: PME Support (R) – Power Management Event Support. This bit field is hardwired to 00H to indicate
that the SiI 0680A does not support PME.
Bit [26]: PPM D2 Support (R) – PCI Power Management D2 Support. This bit is hardwired to 1 to indicate
support for the D2 Power Management State.
Bit [25]: PPM D1 Support (R) – PCI Power Management D1 Support. This bit is hardwired to 1 to indicate
support for the D1 Power Management State.
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Bit [24:22]: Auxiliary Current (R) – Auxiliary Current. This bit field is hardwired to 000B.
Bit [21]: Dev Special Init (R) – Device Special Initialization. This bit is hardwired to 1 to indicate that the SiI
0680A does not require special initialization
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Bit [20]: Reserved (R). This bit is reserved and returns zero on a read.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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