SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.29 EEPROM Memory Address – Command + Status
Address Offset: 98H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Mem Address
This register defines the address and command/status register for EEPROM memory interface in the SiI 0680A. The register
bits are also mapped to Base Address 5, Offset 58H. See Section 9.7.17 for bit definitions.
9.1.30 EEPROM Memory Data
Address Offset: 9CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Memory Data
This register defines the data register for EEPROM memory interface in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset 5CH. See Section 9.7.18 for bit definitions.
9.1.31 IDE0 Task File Timing + Configuration + Status
Address Offset: A0H
Access Type: Read/Write
Reset Value: 0x6515_0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Addr Setup
Count
Active Count
Recovery Count
Reserved
This register defines the task file timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset A0H. See Section 9.7.33 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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SILICONIMAGE [ Silicon image ]
