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SII0680ACLU144 参数 Datasheet PDF下载

SII0680ACLU144图片预览
型号: SII0680ACLU144
PDF下载: 下载PDF文件 查看货源
内容描述: PCI转IDE / ATA [PCI to IDE/ATA]
分类和应用: PC
文件页数/大小: 124 页 / 782 K
品牌: SILICONIMAGE [ Silicon image ]
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SiI0680A PCI to IDE/ATA  
Data Sheet  
Silicon Image, Inc.  
9.1.10 Base Address Register 5  
Address Offset: 24H  
Access Type: Read/Write  
Reset Value: 0x0000_0000  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
Base Address Register 5  
Not Used  
This register defines the addressing of various control functions within the SiI 0680A. This register is enabled when input  
BA5_EN is set to one. See section 3.1.5 for descriptions. The register bits are defined below.  
Bit [31:08]: Base Address Register 5 (R/W). This register defines the Memory Space base address for all  
Silicon Image driver specific functions.  
Bit [07:00]: Base Address Register 5 (R). This bit field is not used and is hardwired to 00H.  
9.1.11 Subsystem ID – Subsystem Vendor ID  
Address Offset: 2CH  
Access Type: Read/Write  
Reset Value: 0x0680_1095  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
Subsystem ID  
Subsystem Vendor ID  
This register defines the Subsystem ID fields associated with the PCI bus. See chapter 8 for details. The register bits are  
defined below.  
Bit [31:16]: Subsystem ID (R) – Subsystem ID.  
Bit [15:00]: Subsystem Vendor ID (R) – Subsystem Vendor ID.  
The value in this bit field is determined by any one of three options:  
1) Bit [31:16]: Subsystem ID (R) – Subsystem ID defaults to 0680AH. Bit [15:00]: Subsystem Vendor  
ID (R) – Subsystem Vendor ID defaults to 1095H.  
2) loaded from an external memory device : If an external memory device – FLASH or EEPROM – is  
present with the correct signature, the PCI Class Code is loaded from that device after reset. The  
correct signature for an EEPROM device is the data pattern 55AAH at addresses [03H:02H] and 55AAH  
at addresses [01H:00H]. The correct signature for a FLASH device is the data pattern AA55H at  
addresses [7FFFFH:7FFFEH] and 55H at address 7FFFCH. See chapter 8 for details.  
3) system programmable : If Bit 0 of the Configuration register (40H) is set, to enables writes, the three  
bytes are system programmable.  
© 2006 Silicon Image, Inc.  
SiI-DS-0069-C  
52  
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