SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.7 Base Address Register 2
Address Offset: 18H
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 2
Not Used
This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below.
•
•
Bit [31:03]: Base Address Register 2 (R/W). This register defines the I/O Space base address for the IDE
Channel #1 task file registers.
Bit [02:00]: Base Address Register 2 (R). This bit field is not used and is hardwired to 001B.
9.1.8 Base Address Register 3
Address Offset: 1CH
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 3
Not
Used
This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below.
•
•
Bit [31:02]: Base Address Register 3 (R/W). This register defines the I/O Space base address for the IDE
Channel #1 Device Control- Alternate Status register.
Bit [01:00]: Base Address Register 3 (R). This bit field is not used and is hardwired to 01B.
9.1.9 Base Address Register 4
Address Offset: 20H
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 4
Not Used
This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below.
•
•
Bit [31:04]: Base Address Register 4 (R/W). This register defines the I/O Space base address for the PCI bus
master registers.
Bit [03:00]: Base Address Register 4 (R). This bit field is not used and is hardwired to 0001B.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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SILICONIMAGE [ Silicon image ]
