S3C4510B
DMA CONTROLLER
31
16 15 14 13 12 11 10 9
8
7
6
5
4 3
2
1
0
M
O
D
E
D C
M N
T
W
S
T
F
S S D S D
A A
B R
S E
B D B
I
F F
[0] Run enable (RE)
0 = Disable DMA operation
1 = Enable DMA operation
1 = DMA is active
[1] Busy status (BS)
0 = DMA is idle
[3:2] Mode selection (MODE)
00 = Software mode (memory to memory)
01 = External EXTDREQ mode (for external devices)
10 = UART0 block
11 = UART1 block
[4:] Destination address direction (DA)
0 = Increase source address 1 = Decrease source address
[5] Source address direction (SA)
0 = Increase source address 1 = Decrease source address
[6] Destination address fix (DF)
0 = Increase/decrease destination address
1 = Do not change destination address (fix)
[7] Source address fix (SF)
0 = Increase/decrease source address
1 = Do not change source address (fix)
[8] Stop interrupt enable (SI)
0 = Do not generate a stop interrupt when DMA stops
1 = Generate a stop interrupt when DMA stops
[9] Four-data burst enable (FB)
0 = Disable 4-data burst mode
1 = Enable 4-data burst mode
[10] Transfer direction (for UART0/UART1 only) (TD)
0 = UART0/UART1 to memory 1 = Memory to UART0/UART1
[11] Single/block mode (SB)
0 = One nXDREQ initiates a single DMA operation
1 = One nXDREQ initiates a whole DMA operation
[13:12] Transfer width (TW)
00 = Byte (8 bits)
10 = Word (32 bits)
01 = Half-word (16 bits)
11 = No use
[14] Continuous mode (CN)
0 = Normal operation
1 = Hold system bus until the whole DMA operation stops
[15] Demand mode (DM)
0 = Normal external DMA mode
1 = Demand mode
Figure 9-2. GDMA Control Register
9-5
SAMSUNG [ SAMSUNG ]
