DMA CONTROLLER
S3C4510B
GDMA SPECIAL REGISTERS
Table 9-1. GDMA Special Registers Overview
Registers
GDMACON0
GDMACON1
GDMASRC0
GDMADST0
GDMASRC1
GDMADST1
GDMACNT0
GDMACNT1
Offset
0xB000
0xC000
0xB004
0xB008
0xC004
0xC008
0xB00C
0xC00C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reset Value
0´ 00000000
0´ 00000000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
GDMA controller channel 0 control register
GDMA controller channel 1 control register
GDMA channel 0 source address register
GDMA channel 0 destination address register
GDMA channel 1 source address register
GDMA channel 1 destination address register
GDMA channel 0 transfer count register
GDMA channel 1 transfer count register
GDMA CONTROL REGISTERS
Table 9-2. GDMACON0 and GDMACON1 Registers
Registers
GDMACON0
GDMACON1
Offset
0xB000
0xC000
R/W
R/W
R/W
Description
Reset Value
0´ 00000000
0´ 00000000
GDMA controller channel 0 control register
GDMA controller channel 1 control register
Table 9-3. GDMA Control Register Description
Bit Name Reset Value
Bit Number
[0]
Run enable/disable
Setting this bit to "1", starts a DMA operation. To stop DMA, you
must clear this bit to "0". You can use the GMA run bit control
address (GDMACON offset address + 0x20) to manipulate this bit.
By using the run bit control address, other GDMA control register
values are not affected.
[1]
Busy status
When DMA starts, this read-only status bit is automatically set to
"1". When it is "0", DMA is idle.
[3:2]
GDMA mode selection
Four sources can initiate a DMA operation: 1) software (memory-
to-memory), 2) an external DMA request (nXDREQ), 3) the UART0
block, and 4) the UART1 block. The mode selection setting
determines which source can initiate a DMA operation at any given
time.
[4]
[5]
Destination address
direction
This bit controls whether the destination address will be
decremented ("1") or incremented ("0") during a DMA operation.
Source address direction This bit controls whether the source address will be decremented
("1") or incremented ("0") during a DMA operation.
9-2
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