S3C4510B
DMA CONTROLLER
9
DMA CONTROLLER
OVERVIEW
The S3C4510B has a two-channel general DMA controller, called the GDMA. The two-channel GDMA performs
the following data transfers without CPU intervention:
— Memory-to-memory (memory to/from memory)
— UART-to-memory (serial port to/from memory)
The on-chip GDMA can be started by software and/or by an external DMA request (nXDREQ). Software can also
be used to restart a GDMA operation after it has been stopped.
The CPU can recognize when a GDMA operation has been completed by software polling and/or when it receives
an appropriate internally generated GDMA interrupt. The S3C4510B GDMA controller can increment or
decrement source or destination addresses and conduct 8-bit (byte), 16-bit (half-word), or 32-bit (word) data
transfers.
System BUS
Mode Selection
GDMA Channel 0
nXDREQ 0
UART0
nDREQ
UART1
nDACK
nXDACK 0
GDMA
Port 14 Data
IOPCON [27:26]
GDMA Channel 1
nDREQ
nDACK
nXDREQ 1
nXDACK 1
GDMA
Mode Selection
Port 15 Data IOPCON [29:28]
Figure 9-1. GDMA Controller Block Diagram
9-1
SAMSUNG [ SAMSUNG ]
