DMA CONTROLLER
Bit Number
S3C4510B
Table 9-3. GDMA Control Register Description (Continued)
Bit Name Reset Value
Demand mode
[15]
Setting this bit speeds up external DMA operations. When [15]="1",
the DMA transfers data when the external DMA request signal
(nXDREQ) is active. The amount of data transferred depends on
how long nXDREQ is active. When nXDREQ is active and DMA
gets the bus in Demand mode, DMA holds the system bus until the
nXDREQ signal becomes non-active. Therefore, the period of the
active nXDREQ signal should be carefully timed so that the entire
operation does not exceed an acceptable interval (as, for example,
in a DRAM refresh operation).
NOTE: In demand mode, you must clear the single/block and
continuous mode control bits to "0".
NOTE: To ensure the reliability of DMA operations, the GDMA control register bits must be configured independently and
carefully.
9-4
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