欢迎访问ic37.com |
会员登录 免费注册
发布采购

S3C4510B 参数 Datasheet PDF下载

S3C4510B图片预览
型号: S3C4510B
PDF下载: 下载PDF文件 查看货源
内容描述: 三星S3C4510B的16位/ 32位RISC微控制器是一款高性价比,高性能的基于以太网的系统微控制器解决方案。 [Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.]
分类和应用: 微控制器以太网
文件页数/大小: 422 页 / 2160 K
品牌: SAMSUNG [ SAMSUNG ]
 浏览型号S3C4510B的Datasheet PDF文件第340页浏览型号S3C4510B的Datasheet PDF文件第341页浏览型号S3C4510B的Datasheet PDF文件第342页浏览型号S3C4510B的Datasheet PDF文件第343页浏览型号S3C4510B的Datasheet PDF文件第345页浏览型号S3C4510B的Datasheet PDF文件第346页浏览型号S3C4510B的Datasheet PDF文件第347页浏览型号S3C4510B的Datasheet PDF文件第348页  
DMA CONTROLLER  
S3C4510B  
GDMA FUNCTION DESCRIPTION  
The following sections provide a functional description of the GDMA controller operations.  
GDMA TRANSFERS  
The GDMA transfers data directly between a requester and a target. The requester and target are memory,UART  
or external devices. An external device requests GDMA service by activating nXDREQ signal. A channel is  
programmed by writing to registers which contain requester address, target address, the amount of data, and  
other control contents. UART, external I/O, or Software(memory) can request GDMA service. UART is internally  
connected to the GDMA.  
STARTING/ENDING GDMA TRANSFERS  
GDMA starts to transfer data after the GDMA receives service request from nXDREQ signal, UART, or Software.  
When the entire buffer of data has been transferred, the GDMA becomes idle. If you want to preform another  
buffer transfer, the GDMA must be reprogrammed. Although the same buffer transfer wii be preformed again, the  
GDMA must be reprogrammed.  
DATA TRANSFER MODES  
Single Mode  
A GDMA request (nXDREQ or an internal request) causes one byte, one half-word, or one word to be transmitted  
if 4-data burst mode is disable state, or four times of transfer width if 4-data burst mode is enable state. Single  
mode requires a GDMA request for each data transfer. The nXDREQ signal can be de-asserted after checking  
that nXDACK has been asserted.  
nXDREQ  
nXDACK  
RD/WR Cycle  
Figure 9-5. External DMA Requests (Single Mode)  
9-8  
 复制成功!