DMA CONTROLLER
S3C4510B
GDMA SOURCE/DESTINATION ADDRESS REGISTERS
The GDMA source/destination address registers contain the 26-bit source/destination addresses for GDMA
channels 0 and 1. Depending on the settings you make to the GDMA control register (GDMACON), the source or
destination addresses will either remain the same, or they will be incremented or decremented.
Table 9-4. GDAMSRC0/1 and GDMADST0/1 Registers
Registers
GDMASRC0
GDMADST0
GDMASRC1
GDMADST1
Offset
0xB004
0xB008
0xC004
0xC008
R/W
R/W
R/W
R/W
R/W
Description
Reset Value
Undefined
Undefined
Undefined
Undefined
GDMA channel 0 source address register
GDMA channel 0 destination address register
GDMA channel 1 source address register
GDMA channel 1 destination address register
31
26 25
0
Source/Destination Address
[25:0] Source/destination address
Figure 9-3. GDMA Source/Destination Address Register
9-6
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