S3C4510B
DMA CONTROLLER
DMA TRANSFER COUNT REGISTERS
The DMA transfer count registers contain the 24-bit current count value of the number of DMA transfers
completed for GDMA channels 0 and 1.
The count value is always decremented by one for each completed DMA operation, regardless of the GDMA data
transfer width or four-data burst mode.
NOTE
At the 4-data burst mode, actual transfer data size will be "Transfer Count x4."
Table 9-5. GDMACNT0/1 Registers
Registers
GDMACNT0
GDMACNT1
Offset
0xB00C
0xC00C
R/W
R/W
R/W
Description
Reset Value
Undefined
Undefined
GDMA channel 0 transfer count register
GDMA channel 1 transfer count register
31
24 23
0
Transfer Count
[23:0] Transfer count
Figure 9-4. DMA Transfer Count Register
9-7