HDLC CONTROLLERS
S3C4510B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
First byte Second byte Third byte
8
7
6
5
4
3
2
1
0
Fourth byte
Station address byte register and MASK register
[31:24] First address byte
[23:16] Second address byte
[15:8] Third address byte
[7:0] Fourth address byte
Figure 8-24. HDLC Station Address and HMASK Register
DMA TX BUFFER DESCRIPTOR POINTER REGISTER
The DMA transmit buffer descriptor pointer register contains the address of the Tx buffer data pointer on the data
to be sent. During a DMA operation, the buffer descriptor pointer is updated by the next buffer data pointer.
Table 8-18. DMA Tx Buffer Descriptor Pointer Registers
Registers
Offset
0x7038
0x8038
R/W
R/W
R/W
Description
Reset Value
0xFFFFFFFF
0xFFFFFFFF
HDMATXPTRA
HDMATXPTRB
DMA Tx Buffer Descriptor Pointer
DMA Tx Buffer Descriptor Pointer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1 0
DMA Tx Buffer Descriptor Pointer
[25:0] DMA Tx Buffer Descriptor Pointer
Figure 8-25. DMA Tx Buffer Descriptor Pointer
8-48
SAMSUNG [ SAMSUNG ]
