S3C4510B
HDLC CONTROLLERS
DMA RX BUFFER DESCRIPTOR POINTER REGISTER
The DMA receive buffer descriptor pointer register contains the address of the Rx buffer data pointer on the data
to be received. During a DMA operation, the buffer descriptor pointer is updated by the next buffer data pointer.
Table 8-19. DMA Rx Buffer Descriptor Pointer Registers
Registers
Offset
0x703c
0x803c
R/W
R/W
R/W
Description
Reset Value
0xFFFFFFFF
0xFFFFFFFF
HDMARXPTRA
HDMARXPTRB
DMA Rx Buffer Descriptor Pointer
DMA Rx Buffer Descriptor Pointer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1 0
DMA Rx Buffer Descriptor Pointer
[25:0] DMA Rx Buffer Descriptor Pointer
Figure 8-26. DMA Rx Buffer Descriptor Pointer
MAXIMUM FRAME LENGTH REGISTER
The HDLC controller checks the length of an incoming frame against the user-defined value in DMA mode. If the
frame received exceeds this register value, the frame is discarded, and FLV(Frame Length Violated) bit is set in
the buffer descriptor belonging to that frame.
Table 8-20. HDMATXCNT and HDMARXCNT Registers
Registers
HMFLRA
HMFLRB
Offset
0x7040
0x8040
R/W
R/W
R/W
Description
Maximum Frame Length
Maximum Frame Length
Reset Value
0xXXXX0000
0xXXXX0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1 0
Maximum Frame Length
[15:0] Maximum Frame Length
Figure 8-27. Maximum Frame Length Register
8-49
SAMSUNG [ SAMSUNG ]
