S3C4510B
HDLC CONTROLLERS
HDLC STATION ADDRESS REGISTERS (HSADR0–3) AND HMASK REGISTER
Each HDLC controller has five 32-bit registers for address recognition: four station address registers and one
mask register. Generally, the HDLC controller reads the address of the frame from the receiver, to check it
against the four station address values, and then masks the result with the user-defined HMASK register. A "1" in
the HMASK register represents a bit position for which an address comparison should occur. A "0" represents a
masked bit position. If you check the address up to four bytes, the HMASK register value should be 0xffffffff.
Dependent on the HMASK register value, the frame's address is compared. If the address is not matched, this
frame is discarded.
Table 8-17. HSADR and HMASK Register
Registers
HSADR0A
HSADR1A
HSADR2A
HSADR3A
HMASKA
HSADR0B
HSADR1B
HSADR2B
HSADR3B
HMASKB
Offset
0x7024
0x7028
0x702c
0x7030
0x7034
0x8024
0x8028
0x802c
0x8030
0x8034
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
HDLC station address 0
HDLC station address 1
HDLC station address 2
HDLC station address 3
HDLC address mask register
HDLC station address 0
HDLC station address 1
HDLC station address 2
HDLC station address 3
HDLC address mask register
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
HMASK
0xFFFFFFFF
HMASK
HSADR0
HSADR1
HSADR2
HSADR3
0xFF0000 00
HSADR0
HSADR1
HSADR2
HSADR3
0xABCDEFGH
0xFFFFFFFF
0xABCDEFGH
0xABCDEFGH
0x55XXXX XX
0x55XXXX XX
0x55XXXX XX
0x55XXXX XX
NOTE:
Recognize one 32-bit address
NOTE:
Recognize a single 8-bit address
and the 32-bit broadcast address
Figure 8-23. Address Recognition
8-47
SAMSUNG [ SAMSUNG ]
