S3C4510B
ETHERNET CONTROLLER
Table 7-6. BDMA Receive Control Register Description (Continued)
Bit Number
Bit Name
Description
[14]
BDMA Rx enable (BRxEn)
When the Rx enable bit is set to "1", the BDMA Rx block is
enabled. Even if this bit is disabled, the MAC will receive Rx
data until the MAC Rx FIFO overflows (as long as the FIFO is
not empty and the MAC Rx is enabled). This bit is
automatically disabled in the following cases: 1) if the next
frame pointer is Null, or 2) if the owner bit is zero, and the
BRxSTSKO bit is set.
NOTE: The frame descriptor start address pointer must be
assigned before the BDMA Rx enable bit is set.
[15]
[16]
BDMA Rx reset (BRxRS)
Set this bit to "1" to reset the BDMA Rx block.
BDMA Rx buffer empty
Set this bit is "1" to enable the Rx buffer empty interrupt.
interrupt enable (BRxEmpty)
[17]
BDMA Rx early notify
interrupt enable (BRxEarly)
Set this bit to "1" to enable the Rx early notify interrupt. The
function of this interrupt is to note the length of a data frame
that is being received from its frame length field.
7-27
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