ETHERNET CONTROLLER
S3C4510B
Buffered DMA Receive Control Register
The buffered DMA receive control register, BDMARXCON, is described in Tables 7-5 and 7-6 below.
Table 7-5. BDMA RXCON Register
Register
Offset Address
R/W
Description
Rest Value
BDMARXCON
0x9004
R/W
Buffered DMA receive control register
0x00000000
Table 7-6. BDMA Receive Control Register Description
Bit Number
Bit Name
Description
[4:0]
BDMA Rx burst size
(BRxBRST)
(Word size + 1) of data bursts requested in BDMA mode. If
the BRxBRST is zero, the burst size is one word. If the
BRxBRST is 31, the burst size is 32 words.
[5]
[6]
[7]
[8]
BDMA Rx stop/skip frame by This bit determines whether the BDMA Rx controller issues an
owner bit (BRxSTSKO)
interrupt, if enabled, or skips the current frame and goes to the
next frame descriptor (assuming BDMA is not the owner).
BDMA Rx memory address
inc/dec (BRxMAINC)
This bit determines whether the address is incremented or
decremented. If this bit is set to "1", the address will be
incremented.
BDMA Rx every received
frame interrupt enable
(BRxDIE)
This bit enables the BDMA Rx every received frame interrupt
which is generated by the BDMA controller each time is moves
a complete data frame into memory.
BDMA Rx Null list interrupt
enable (BRxNLIE)
This bit enables the BDMA Rx null list interrupt which indicates
that the receive frame descriptor start address pointer,
BDMARXPTR, in the BDMA Rx block has a null (0x00000000)
address.
[9]
[10]
BDMA Rx not owner interrupt This bit enables the BDMA Rx not owner interrupt when the
enable (BRxNOIE)
ownership bit of the current frame does not belong to the
BDMA controller, and if the BRxSTSKO bit is set.
BDMA Rx maximum size over This bit enables the BDMA Rx maximum size over interrupt
interrupt enable (BRxMSOIE) when the received frame size is larger than the value in
receive frame maximum size register.
[11]
BDMA Rx Big/Little Endian
(BRxLittle)
This bit determines whether the data is stored in Little- or Big-
Endian format. If it is set to "1", word swapping will take place
between the receive buffer and the system data bus.
[13:12]
BDMA Rx word alignment
(BRxWA)
The Rx word alignment bits determine how many bytes are
invalid in the first word of each data frame. These invalid bytes
are inserted when the word is assembled by the BDMA
controller. "00" = No invalid bytes, "01" = 1 invalid byte, "10" =
2 invalid bytes, and "11" = 3 invalid bytes.
7-26
SAMSUNG [ SAMSUNG ]
