S3C4510B
ETHERNET CONTROLLER
BDMA Transmit Frame Descriptor Start Address Register
Table 7-7. BDMATXPTR Register
R/W Description
R/W Buffered DMA transmit control register
Registers
Offset
Reset Value
0xFFFFFFFF
BDMATXPTR
0x9008
Table 7-8. BDMA Transmit Frame Descriptor Start Address Register Description
Bit Number
Bit Name
Description
[25:0]
BDMA transmit frame
descriptor start address
The BDMA transmit frame descriptor start address register
contains the address of the frame descriptor on the frame to
be sent. During a BDMA operation, this start address pointer is
updated to the next frame address.
BDMA Receive Frame Descriptor Start Address Register
Table 7-9. BDMARXPTR Register
R/W Description
R/W Buffered DMA transmit control register
Registers
Offset
Reset Value
BDMARXPTR
0x900C
0xFFFFFFFF
Table 7-10. BDMA Receive Frame Descriptor Start Address Register Description
Bit Number
Bit Name
Description
[25:0]
BDMA receive frame
descriptor start address
The BDMA receive frame descriptor start address register
contains the address of the frame descriptor on the frame to
be saved. During a BDMA operation, this start address pointer
is updated to the next frame address.
7-29
SAMSUNG [ SAMSUNG ]
