S3C4510B
ETHERNET CONTROLLER
Buffered DMA Transmit Control Register
The buffered DMA transmit control register, BDMATXCON, is described in Tables 7-3 and 7-4 below.
Table 7-3. BDMATXCON Register
Registers
Offset
R/W
Description
Reset Value
BDMATXCON
0x9000
R/W
Buffered DMA transmit control register
0x00000000
Table 7-4. BDMA Transmit Control Register Description
Bit Number
Bit Name
Description
[4:0]
BDMA Tx burst size
(BTxBRST)
(Word size + 1) of data bursts requested in BDMA mode.
If the BTxBRST is zero, the burst size is one word.
If the BTxBRST is 31, the burst size is 32 words.
[5]
BDMA Tx stop/skip frame by
owner bit (BTxSTSKO)
This bit determines whether the BDMA Tx controller issues an
interrupt, if enabled, or skips the current frame and goes to the
next frame descriptor (assuming BDMA is not the owner).
[6]
[7]
Reserved
Not applicable.
BDMA Tx complete to send
Setting this bit enables the BDMA Tx complete to send contol
control packet interrupt enable packet interrupt when the MAC has finished sending the
(BTxCCPIE)
control packet.
[8]
[9]
BDMA Tx Null list interrupt
enable (BTxNLIE)
This bit enables the BDMA Tx Null list interrupt which indicates
that the transmit frame descriptor start address pointer,
BDMATXPTR, in the BDMA Tx block has a null (0x00000000)
address.
BDMA Tx not owner interrupt This bit enables the BDMA Tx not owner interrupt when the
enable (BTxNOIE)
ownership bit of the current frame does not belong to the
BDMA controller, and if the BTxSTSKO bit is set.
[10]
BDMA Tx buffer empty
Set this bit is "1" to enable the Tx buffer empty interrupt.
interrupt enable (BTxEmpty)
[13:11]
BDMA transmit to MAC Tx
start level (BTxMSL)
These bits determine when the new frame data in BDMA Tx
buffer can be moved to the MAC Tx FIFO when a new frame
arrives.
000 means no wait, 001 means wait to fill 1/8 of the BDMA Tx
buffer, 010 means wait to fill 2/8 of the buffer, 011 for 3/8 and
1xx for 4/8.
NOTE: If the last data of the frame arrives in BDMA Tx buffer,
the data transfer from the BDMA Tx buffer to the MAC Tx
FIFO starts immediately, regardless of the level of these bits.
7-23
SAMSUNG [ SAMSUNG ]
