ETHERNET CONTROLLER
S3C4510B
ETHERNET CONTROLLER SPECIAL REGISTERS
The special registers used by the S3C4510B ethernet controller are divided into two main groups:
— BDMA control and status registers
— MAC control and status registers
BDMA CONTROL AND STATUS REGISTERS
All registers that contain a memory address must store the address in a word-aligned format.
Table 7-2. BDMA Control and Status Registers
Registers
BDMATXCON
BDMARXCON
BDMATXPTR
BDMARXPTR
BDMARXLSZ
BDMASTAT
CAM
Offset
0x9000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Description
Reset Value
Buffered DMA transmit control register
Buffered DMA receive control register
Transmit frame descriptor start address
Receive frame descriptor start address
Receive frame maximum size
Buffered DMA status
0x00000000
0x00000000
0xFFFFFFFF
0xFFFFFFFF
Undefined
0x9004
0x9008
0x900C
0x9010
0x9014
0x00000000
Undefined
0x9100–0x917C
0x9200–0x92FC
CAM content (32 words)
BDMATXBUF
(1)
R/W
BDMA transmit (Tx) buffer (64 words)
for test mode addressing only
Undefined
BDMARXBUF
(1)
0x9800–0x98FC
0x9900–0x99FC
R/W
BDMA receive (Rx) buffer (64 words)
for test mode addressing only
Undefined
NOTES:
1. For testing, you can read the BDMA Tx/Rx buffer directly. The BDMA receive buffer has a 64 word by 33 bit size.
The highest bit, [32], indicates the data frame boundary, as shown in the following illustration:
32 31
0
0x9800
0x98FC
0x9900
0x99FC
EOF (End of Frame); Boundary of frame data.
Figure 7-11. End of Frame Bit
2. You can access the EOF bit by reading the address range, 0x9800-0x98FC (read into LSB bit 0).
7-22
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