OneNAND512Mb(KFG1216U2B-xIB6)
3.5 Data Protection During Power Down Operation
FLASH MEMORY
See Timing Diagram 6.17
The device is designed to offer protection from any involuntary program/erase during power-transitions.
RP pin which provides hardware protection must be kept at VIL before Vcc drops to 1.8V.
3.6
Load Operation
See Timing Diagrams 6.10
The Load operation is initiated by setting up the start address from which the data is to be loaded. The Load command is issued in
order to initiate the load.
During a Load operation, the device:
-Transfers the data from NAND Flash array into the BufferRAM
-ECC is checked and any detected and corrected error is reported in the status response as well as
any unrecoverable error.
Once the BufferRAM has been filled, an interrupt is issued to the host so that the contents of the BufferRAM can be read. The read
from the BufferRAM can be an asynchronous read mode or synchronous read mode. The status information related to load operation
can be checked by the host if required.
The device has a dual data buffer memory architecture (DataRAM0, DataRAM1), each 2KB in size. Each DataRAM buffer has 4
Sectors. The device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to
the other data buffer. Refer to the information for more details in section 3.9.1, "Read-While-Load Operation".
Load Operation Flow Chart Diagram
Write ’Load’ Command
Start
Add: F220h
DQ=0000h or 0013h
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Wait for INT register
low to high transition
Write ’FPA, FSA’ of Flash
Add: F241h DQ[15]=INT
Add: F107h DQ=FPA, FSA
Read Controller
Status Register
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Add: F240h DQ[10]=Error
Write 0 to interrupt register1)
Add: F241h DQ=0000h
NO
DQ[10]=0?
YES
Map Out
Host reads data from
DataRAM
Read completed
Note 1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
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