Preliminary
K5A3x80YT(B)C
MCP MEMORY
Flash SWITCHING WAVEFORMS
Hardware Reset/Read Operations
tRC
Address Stable
Address
tAA
CE
F
tRH
tRP
tRH
tCE
RESET
tOH
High-Z
Output Valid
Outputs
70ns
80ns
Unit
Parameter
Symbol
Min
70
-
Max
Min
80
-
Max
Read Cycle Time
tRC
tAA
tCE
tOH
tRP
tRH
-
70
70
-
-
80
80
-
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
-
-
Output Hold Time from Address, CE or OE
0
0
F
RESET Pulse Width
500
50
-
500
50
-
RESET High Time Before Read
-
-
Revision 0.0
November 2002
- 31 -