Preliminary
K5A3x80YT(B)C
MCP MEMORY
Flash SWITCHING WAVEFORMS
Read Operations
tRC
Address Stable
Address
tAA
CE
F
tOE
tDF
OE
tOEH1
WE
tCE
tOH
HIGH-Z
HIGH
HIGH-Z
Outputs
RY/BY
Output Valid
70ns
80ns
Parameter
Symbol
Unit
Min
Max
-
Min
Max
-
Read Cycle Time
tRC
tAA
tCE
tOE
tDF
70
-
80
-
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
Output Enable Time
70
70
25
16
80
80
25
16
-
-
-
-
CE & OE Disable Time (1)
-
-
F
Output Hold Time from Address, CE or OE
tOH
0
0
-
-
0
0
-
-
ns
ns
F
OE Hold Time
tOEH1
NOTE: 1. Not 100% tested.
Revision 0.0
November 2002
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