256M GDDR3 SDRAM
K4J55323QG
WRITE Burst
T0
T1
T2
T3
T3n
T4
T4n
T5
T5n
T6
/CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
Bank a,
Col b
tDQSS(NOM)
tDQSS
WDQS
DI
b
DQ
DM
t
DQSS(MIN)
WDQS
tDQSS
DI
DQ
DM
b
t
DQSS(MAX)
WDQS
tDQSS
DI
b
DQ
DM
DON’T CARE
TRANSITIONING DATA
1. DI b = data-in for column b.
NOTE :
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. A burst of 4 is shown.
4. A8 is LOW with the WRITE command (auto precharge is disabled).
5. Write latency is set to 4
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Rev. 1.1 November 2005