256M GDDR3 SDRAM
K4J55323QG
Random READ Accesses
T0
T1
T2
T8
T8n
T9
T9n
T10
T10n
/CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank a,
Col n
Bank a,
Col b
CL = 8
RDQS
DQ
DO
n
DO
n
DO
n
DO
n
DO
b
T0
T1
T7
T8
T8n
T9
T9n
T15
T15n
/CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank a,
Col n
Bank a,
Col b
CL = 8
RDQS
DQ
DO
n
DO
n
DO
n
DO
n
DO
b
DON’T CARE
TRANSITIONING DATA
1. DO n (or x or b or g) = data-out from column n (or column x or column x or column b or column g).
2. Burst length = 4
NOTE :
3. n’ or x or b’ or g’ indicates the next data-out following DO n or DO x or DO b OR DO g, respectively
4. READs are to an active row in any bank.
5. Shown with nominal tAC and tDQSQ.
6. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
29 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
