256M GDDR3 SDRAM
K4J55323QG
Random WRITE Cycles
T0
T1
T2
T3
T3n
T4
T4n
T5
T5n
T6
T6n
T7
/CK
CK
COMMAND
ADDRESS
WRITE
NOP
WRITE
NOP
WRITE
NOP
NOP
NOP
Bank
Col b
Bank
Col x
Bank
Col g
tDQSS (NOM)
WDQS
DQ
DI
b
DI
b
DI
b
DI
b
DI
x
DI
x
DI
x
DI
x
DI
g
DI
g
DM
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DI b, etc. = data-in for column b, etc.
2. b: etc. = the next data - in following DI b. etc., according to the programmed burst order.
3. Programmed burst length = 4 cases shown.
4. Each WRITE command may be to any bank.
5. Last write command will have the rest of the nibble on T8 and T8n
6. Write latency is set to 3
36 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
