256M GDDR3 SDRAM
K4J55323QG
READ to PRECHARGE
T0
T1
T2
T8
T8n
T9
T9n
T10
/CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
Bank a,
(a or all)
Bank a,
Col n
Bank a,
Row
CL = 8
tRP
RDQS
DQ
DO
n
T0
T1
T7
T8
T8n
T9
T13
/CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
Bank a,
(a or all)
Bank a,
Col n
Bank a,
Row
tRP
CL = 8
RDQS
DQ
DO
n
DON’T CARE
TRANSITIONING DATA
NOTE :
1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Three subsequent elements of data-out appear in the programmed order following DQ b.
5. Shown with nominal tAC and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecutive READs.
7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
31 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
