256M GDDR3 SDRAM
K4J55323QG
Nonconsecutive WRITE to WRITE
T0
T1
T2
T3
T3n
T4
T4n
T5
T5n
T6
T6n
T7
/CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
Bank,
Col b
Bank,
Col n
tDQSS (NOM)
WDQS
DQ
DI
b
DI
n
DON’T CARE
DM
DON’T CARE
TRANSITIONING DATA
1. DI b, etc. = data-in for column b, etc.
NOTE :
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. burst of 4 is shown.
5. Each WRITE command may be to any bank.
6. Write latency is set to 3
35 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
