256M GDDR3 SDRAM
K4J55323QG
READ Burst
T0
T7
T8
T8n
T9
T9n
T10
T11
/CK
CK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
Bank a,
Col n
ADDRESS
RDQS
CL = 8
DO
n
DQ
T0
T7
T8
T9
T9n
T10
T11
/CK
CK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
Bank a,
Col n
ADDRESS
RDQS
DQ
CL = 9
DO
n
DON’T CARE
TRANSITIONING DATA
1. DO n=data-out from column n.
NOTE :
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Shown with nominal tAC and tDQSQ.
5. RDQS will start driving high 1/2 clock cycle prior to the first falling edge.
26 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG ]
