64M DDR SDRAM
K4D623238B-GC
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A0 ~ A10 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,
addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A 8 is
used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
Address Bus
BA1
BA0
0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU
RFU
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
Burst Type
A3 Type
DLL
Test Mode
A7
A8
0
DLL Reset
No
mode
0
1
Sequential
Interleave
0
1
Normal
Test
1
Yes
Burst Length
CAS Latency
Burst Type
A2
A1
A0
BA0
An ~ A0
Sequential
Reserve
2
Interleave
Reserve
2
A6
0
A5
0
A4
0
Latency
0
1
MRS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
EMRS
0
0
1
4
4
0
1
0
8
8
0
1
1
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Reserve
Reserve
Reserve
Full page
Reserve
Reserve
Reserve
Reserve
1
0
0
4
1
0
1
5
1
1
0
Reserved
Reserved
1
1
1
MRS Cycle
0
1
2
3
4
5
6
7
8
CK, CK
Precharge
All Banks
Any
Command
Command
NOP
NOP
NOP
MRS
NOP
NOP
NOP
tRP
tMRD=2 tCK
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
- 8 -
Rev. 1.4 (Sep. 2002)
SAMSUNG [ SAMSUNG ]
