Rx5C348A/B
restart of oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data
after power-on or a drop in supply voltage.
* When the XSTP bit is set to 1, all bits will be reset to 0 in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, stopping the output from /INTR pin and starting the output of 32.768-kHz
clock pulses from the 32KOUT pin.
* The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely,
setting the XSTP bit to 1 causes no event.
* It is recommendable to frequently check the XSTP bit for setting errors or data garbles, which may
seriously affect the operation of the Rx5C348A/B.
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Rev.2.01
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RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
